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3.2.1.1
X Data Memory
The on-chip X data RAM is a 16-bit-wide, internal, static memory occupying the lowest
2048 locations (0–$7FF) in X memory space. The on-chip peripheral registers occupy
the top 64 locations of the X data memory ($FFC0–$FFFF). The On-Chip X Data Mem-
ory addresses are received from the X address Bus one (XAB1) and X address Bus two
(XAB2) and data transfers occur on the X data bus (XDB) and global data bus (GDB).
Two reads, one read, or one write can be performed during one instruction cycle on the
internal data memory. The on-chip peripherals occupy the top 64 locations in the X data
memory space (X:$FFC0-X:$FFFF). X memory may be expanded off-chip for a total of
65,536 addressable locations.
3.2.1.2
Program Memory
On-chip program memory consists of a 12288 location by 16-bit, high-speed ROM that is
enabled/disabled by the MA and MB bits in the OMR. The On-Chip Program Memory ad-
dresses are received from the program control logic (usually the program counter) or from
the address ALU on the PAB. Off-chip program memory may be written using move pro-
gram memory (MOVEM) instructions. The first 64 locations of the program memory
($0000–$003F) are reserved for interrupt vectors. The program memory may be expand-
ed off-chip for a total of 65,536 addressable locations.
3.2.1.3
Chip Operating Modes
The DSP operating modes determine the memory maps for program and data memories
and the startup procedure when the DSP leaves the reset state. The MODA, MODB, and
MODC pins are sampled as the DSP leaves the reset state, and the initial operating mode
of the DSP is set accordingly. After the reset state is exited, the MODA and MODB pins
become general-purpose interrupt pins, IRQA, and IRQB. One of three initial operating
modes is selected: single chip, normal expanded, or development. Chip operating modes
can be changed by writing the operating mode bits (MB, MA) in the OMR. Changing op-
erating modes does not reset the DSP. It is desirable to disable interrupts immediately
before changing the OMR to prevent an interrupt from going to the wrong memory loca-
tion. Also, one no-operation (NOP) instruction should be included after changing the OMR
to allow for remapping to occur.
3.2.1.3.1
Single-chip Mode (Mode 0)
Mode 0 is one of two single-chip modes which have internal program memory enabled (see
Figure 3-2). This mode can be entered by either grounding both mode pins and resetting
the chip or by writing to the OMR and changing the MA and MB bits. The memory maps
for Mode 0 and Mode 1 are identical. The difference between Mode 0 and Mode 2 is the
3 - 10
OPERATING MODES AND MEMORY SPACES
ROM MEMORY DESCRIPTION
MOTOROLA
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