Motorola DSP56156 Manual page 241

15 14 13
RIE TIE RE
7 6 5
SHFD SCKP SCKD FSD1
8.12.1 CRB Serial Output Flag 0 and 1 (OF0, OF1) Bit 0, 1
When SSI is in the synchronous mode and when the FSD0 and FSD1 bits are set (indi-
cating that pins SC0x and SC1x are used as output flags) data present in OF0 and OF1
will be written to SC0x and SC1x at the beginning of the frame in normal mode or at the
beginning of the next valid time slot in network mode.
8.12.2 Transmit and Receive Frame Sync Directions - (FSD0, FSD1) Bit 2,4
The Frame Sync Direction bits (FSD1, FSD0) determine the direction of SC1x and SC0x
and whether the frame sync or the flags are used. If FSD0=0 and FSD1=0, then both pins
are inputs. If FSD0=1 and FSD1=0, then SC1x is an input and SC0x is an output. If
FSD1=1, then both pins are outputs. SC0x and SC1x are both used as frame syncs (SC0x
only if SYN=1) and SSISR flag inputs. Output pins reflect either the frame sync (FSD0=0
and FSD1=1) or the flags (FSD0=1, FSD1=1, & SYN = 1). Table 8-4 shows the functions
of the two pins SC1x and SC0x according to the definition of CRB flags SYN, FSD1 and
FSD0.
CRB Flags
SYN FSD0 FSD1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
RFS: Receive Frame Sync; TFS: Transmit Frame Sync; FS: Frame Sync
8 - 16 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSI CONTROL REGISTER B (CRB)
12 11 10
TE MOD SYN
4 3 2
A/MU FSD0
Figure 8-9 SSI Control Register B
Table 8-4 Function of SC1x and SC0x Pins
Mode
Async
Async
Async
-
Sync
Sync
-
Sync
9 8
FSI FSL
1 0
OF1 OF0
SC1x SC0x
RFS in TFS in
RFS out TFS out
RFS in TFS out
- -
- FS in
- FS out
- -
F1 out F0 out
READ-WRITE
SSIx CONTROL
REGISTER B (CRB)
SSI0 ADDRESS $FFD1
SSI1 ADDRESS $FFD9
Comments
Illegal for on-demand
(Reserved)
Illegal for on-demand
(Reserved)
Flags used for sync as
in Figure 8-5
MOTOROLA