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Revision History
Code No.
Page
412925000
All
New establishment
412925001
23-2
23 Package
Corrected the description of the EXPOSED DIE PAD in Figure 23.2.
* The potential of the EXPOSED DIE PAD is the same as that of the substrate potential (V
412925002
1-3
1.1 Features
Modified Table 1.1.
Shipping form: A JEITA names was added to the package name.
2-10
2.3.4 Operations
Oscillation start time and oscillation stabilization waiting time
Added the following description:
The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16,384 OSC1CLK
clocks or more.
3-3
3.3.3 List of debugger input/output pins
Added notes.
Notes: • Do not drive the DCLK pin with a high level from outside (e.g. pulling up with a resistor). Also,
4-3
4.3.3 Flash Programming
Modified Figure 4.3.3.1.
C
Added the following description:
When supplying the V
6-16
6.7.6 Pd Port Group
Modified Table 6.7.6.1.
PDIOEN register: PDOEN[4:3], [1:0] → PDOEN[4:0]
8-4
8.4 Control Registers
WDT Control Register
Corrected the description of the WDTRUN[3:0] bit.
Bits 3–0 WDTRUN[3:0]
9-2
9.3.2 Theoretical Regulation Function
Corrected Step 1.
1. Measure f
9-4
9.4.2 Real-Time Clock Counter Operations
Corrective operation when a value out of the effective range is set
Added a note.
Note: Do not set the RTCMON.RTCMOL[3:0] bits to 0x0 if the RTCMON.RTCMOH bit = 0.
9-6
9.6 Control Registers
RTC Control Register
Bits 14–8 RTCTRM[6:0]
Added a note.
Notes: ...
9-11
9.6 Control Registers
RTC Month/Day Register
Bit 12
Bits 11–8 RTCMOL[3:0]
Added a note.
Notes: ...
10-3
10.4.1 SVD Control
Starting detection
Corrected Step 4.
4. ...
of the IC.
do not connect (short-circuit) between the DCLK pin and another GPIO port. In the both cases,
the IC may not start up normally due to unstable pin input/output status at power on.
• Do not drive the DSIO pin with a low level from outside, as it generates a debug interrupt that
puts the CPU into DEBUG mode.
was changed to that must always be connected.
VPP
power source, be sure to connect C
PP
These bits control WDT to run and stop.
0xa (WP):
Values other than 0xa (WP): Run
0xa (R):
0x0 (R):
and calculate the frequency tolerance correction value
OSC1
"m [ppm] = -{(f
- 32,768 [Hz]) / 32,768 [Hz]} × 10
OSC1
(Eq. 9.1) m: OSC1 frequency tolerance correction value [ppm]
• Writing 0x00 to the RTCCTL.RTCTRM[6:0] bits sets the RTCCTL.RTCTRMBSY bit to 1 as well.
However, no correcting operation is performed.
RTCMOH
• Be sure to avoid setting the RTCMON.RTCMOH/RTCMOL[3:0] bits to 0x00.
- Set the SVDINTE.SVDIE bit to 1.
Contents
VPP
Stop
Idle
Running
6
."
REVISION HISTORY
) on the back
SS
for stabilizing the V
voltage.
PP
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