Revision History - Epson S1C31W74 Technical Manual

Revision History

Code No. Page
413374500 All New establishment
413374501 Whole Corrected the Cortex
manual System control register
Vector table offset register
System handler priority registers
Interrupt priority registers
Correcred the Cortex
Cortex
COU core → CPU
MSCPROT (register name) → SYSPROT
1-2 to 3 1.1 Fetures
Added the following annotations to Table 1.1.1.
I 2
*1 The input filter in I2C (SDA and SCL inputs) does not comply with the standard for removing noise
*2 SLEEP mode refers to deep sleep mode in the Cortex
Modified Table 1.1.1.
Power supply voltage: V
Shipping form: A JEITA name was added to the package name.
1-4, 5, 8 1.3 Pins
Modified Figures 1.3.1.1 and 1.3.2.1, and Table 1.3.3.1.
The ENVPP output function was added to the P26 pin.
2-9 2.3.4 Operations
Oscillation start time and oscillation stabilization waiting time
Added the following description:
The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16,384 OSC1CLK
clocks or more.
2-13 2.4.2 Transition between Operating Modes
SLEEP mode
Added the following description:
The RAM retains data even in SLEEP mode.
3-2 Added a new section.
3.4 Reference Documents
4-2 4.3.1 Flash Memory Pin
Added (ENVPP) to Table 4.3.1.1.
Added a note.
Notes: ...
4-3 4.3.3 Flash Programming
Corrected the description.
The Flash memory supports on-board programming, so it can be programmed using a flash loader. The
V
Be sure to connect C
supplied externally or for generating the voltage when the internal power supply is used.
The V
to disconnect the wire when using Bridge Board (S5U1C31001L) to supply the V
Board controls the power supply so that it will be supplied during Flash programming only.
Notes: • The Flash programming requires a 2.4 V or higher V
® -M0+ register names.
® -M0+ manual names.
® -M0+ Technical Reference Manual → ARM
C (I2C)
*1
spikes less than 50 ns.
SLEEP mode.
operating voltage for Flash programming 2.7 to 3.6 V → 2.4 to 3.6 V
DD
• The ENVPP pin outputs a control signal to the Bridge Board (S5U1C31001L) during Flash
programming. Although this pin can be used as a general-purpose input/output port, take an
effect of this signal on external circuits into consideration.
voltage can be supplied from either an external power supply or the internal voltage booster.
PP
between the V
VPP
pin must be left open except when programming the Flash memory. However, it is not necessary
PP
• Be sure to avoid using the V
Contents
→ Cortex ® -M0+ System Control Register
or
Cortex ® -M0+ Application Interrupt and Reset Control Register
→ Cortex ® -M0+ Vector Table Offset Register (VTOR)
→ Cortex ® -M0+ System Handler Priority Registers
→ Cortex ® -M0+ Interrupt Priority Registers
® v6-M Architecture Reference Manual、
Cortex ® -M0+Technical Reference Manual、
or
the documents introduced in Section 3.4, such as
"Cortex ® -M0+ Devices Generic User Guide"
® -M0+ processor. The RAM retains data even in
and V pins for stabilizing the voltage when the V
SS PP
voltage.
DD
pin output for driving external circuits.
PP
REVISION HISTORY
voltage is
PP
voltage, as Bridge
PP