Revision History - Epson S1C17M12 Technical Manual

Revision History

Code No. Page
413454300 All New establishment
413454301 1-2 1.1 Features
Added the following annotations to Table 1.1.1.
I 2
*1 The input filter in I2C (SDA and SCL inputs) does not comply with the standard for removing noise
SLEEPモード
*2 The RAM retains data even in SLEEP mode.
Modified Table 1.1.1.
Shipping form: A JEITA name was added to the package name.
2-10 2.4.2 Transition between Operating Modes
SLEEP mode
Added the following description:
The RAM retains data even in SLEEP mode.
3-3 3.3.3 List of debugger input/output pins
Added a note.
Notes: ...
6-17 6.7.6 Pd Port Group
Modified Table 6.7.6.1.
PDIOEN register: PDOEN[4:3], [1:0] → PDOEN[4:0]
9-3 9.4.1 SVD3 Control
Starting detection
Corrected Step 4.
4. ...
13.1 13.1 Overview
Added the following description:
• The input filter for the SDA and SCL inputs does not comply with the standard for removing noise
19-1 19.1 Absolute Maximum Ratings
Modified the characteristics table.
V
19-1 19.2 Recommended Operating Conditions
Added "(V
*1 The potential variation of the V
*4 The component values should be determined after evaluating operations using an actual mounting
19-4 19.4 System Reset Controller (SRC) Characteristics
Reset hold circuit characteristics
Modified the characteristics table.
t
RSTR
19-5 19.6 Flash Memory Characteristics
Added an annotation.
*1 The potential variation of the V
20-1 20 Basic External Connection Diagram
2.4–5.5 V (V
*1 For Flash programming
21-1 21 Package
A JEITA name was added to the package name.
AP-A-7 Appendix A List of Peripheral Circuit Control Registers
PDIOEN (Pd Port Enable Register)
Modified the register table.
PDIOEN register: PDOEN[4:3], [1:0] → PDOEN[4:0]
C (I2C)
*1
spikes less than 50 ns.
*2
• Do not drive the DSIO pin with a low level from outside, as it generates a debug interrupt that
puts the CPU into DEBUG mode.
- Set the SVDINTE.SVDIE bit to 1.
spikes less than 50 ns.
: #RESET was added to the condition.
I
= V = 0 V) *1" and the following annotations:
SS SS2
ground potential of the MCU mounting board while the Flash is being programmed, as it affects the
Flash memory characteristics (programming count).
board.
: Min. = 0.5 ms, Max. = 0.9 ms
ground potential of the MCU mounting board while the Flash is being programmed, as it affects the
Flash memory characteristics (programming count).
) and an annotation were added.
DD
Contents
voltage should be suppressed to within ±0.3 V on the basis of the
SS
voltage should be suppressed to within ±0.3 V on the basis of the
SS
REVISION HISTORY