Revision History - Epson S1C17W22 Technical Manual

Revision History

Code No. Page
412690400 All New establishment
412690401 1-4 Block diagram: Figure 1.2.2 S1C17W23 Block Diagram
Modified the figure (Analog input/output direction)
2-18 CLG: CLG System Clock Control Register - Bit 15 WUPMD
(Old) No description
(New) Notes: ...
6-15 PPORT: P4 Port Interrupt Control Register
(Old) P4IEN[4:0]
(New) P4IE[4:0]
20-1 ADC12A: Figure 20.1.1 ADC12A Configuration
Modified the figure (Analog input/output direction)
20-2 ADC12A: Figure 20.2.2.1 Connections between ADC12A and External Devices
Modified the figure (Analog input/output direction)
21-1 OPCMP: Figure 21.1.1 OPCMP Configuration
Modified the figure (Analog input/output direction)
23-17 Electrical characteristics: 12-bit A/D converter (ADC12A) characteristics
(Old) Differential nonlinearity Max. = ±2
(New) Differential nonlinearity Max. = ±3
AP-A-9 List of peripheral circuit control registers: P4 Port Interrupt Control Register
(Old) P4IEN[4:0]
(New) P4IE[4:0]
412690402 1-1 Features: Table 1.1.1 Features
(Old) Watchdog timer (WDT) | Generates NMI or watchdog timer reset.
(New) Watchdog timer (WDT) | Generates watchdog timer reset.
2-3 Power Supply, Reset, and Clocks: Automatic mode
(Old) 4. When the slp instruction is executed in normal mode (only OSC1 operates during SLEEP)
(New) 4. When the slp instruction is executed in normal mode (only OSC1 operates during SLEEP)
2-5 Power Supply, Reset, and Clocks: Watchdog timer reset
(Old) Setting the watchdog timer into reset mode will issue a reset request when the counter overflows.
(New) The watchdog timer issues a reset request when the counter overflows.
2-15 Power Supply, Reset, and Clocks: Canceling HALT or SLEEP mode
(Old) • NMI from the watchdog timer
(New) • NMI
2-21 Power Supply, Reset, and Clocks: CLG OSC3 Control Register
Modified the register table (OSC3WT[2:0]: Initial = 0x6 → 0x0)
5-1 ITC: Figure 5.1.1 ITC Configuration
Modified the figure (The watchdog timer block was deleted. → GND)
5-1, 5-3 ITC: Table 5.2.1 Vector Table
(Old) TTBR + 0x00 | • Watchdog timer overflow *2
(New) TTBR + 0x00 | • Watchdog timer overflow
5-4 ITC: Peripheral Circuit Interrupt Control
(Old) Note: To prevent occurrence of unnecessary interrupts, always clear the corresponding interrupt
(New) Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be
ITC: NMI
(Old) The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This inter-
(New) This IC cannot generate non-maskable interrupts (NMI).
5-6 ITC: ITC Interrupt Level Setup Register 8
Modified the register table ((S1C17W23 only) was deleted.)
• When the CLKSCLK.WUPMD bit = 1, ... set the CLKSCLK.WUPMD bit to 0.
After a lapse of 1 ms from transition to SLEEP mode, the hardware switches from normal mode
to economy mode and sets the PWGINTF.MODCMPIF bit to 1.
After a lapse of 1 ms from transition to SLEEP mode, the hardware switches from normal mode
to economy mode and sets the PWGINTF.MODCMPIF bit to 1.
Note: The IC does not enter economy mode if a clock source other than OSC1 is active when the
slp instruction is executed. Therefore, stop clock sources other than OSC1 before executing
the slp instruction.
TTBR + 0x08 | Watchdog timer overflow *2
*2 Either reset or NMI can be selected as the watchdog timer interrupt with software.
TTBR + 0x08 | –
(Note *2 was deleted.)
flag before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the
interrupt handler routine.
cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating
the interrupt handler routine.
rupt takes precedence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.
Contents
REVISION HISTORY