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5 INTERRUPT CONTROLLER (ITC)
Note: Before changing the interrupt level, make sure that no interrupt of which the level is changed can
be generated (the interrupt enable bit of the peripheral circuit is set to 0 or the peripheral circuit
is deactivated).
5.4.3 Conditions to Accept Interrupt Requests by the CPU
The CPU accepts an interrupt request sent from the ITC when all of the following conditions are met:
• The IE (Interrupt Enable) bit of the PSR has been set to 1.
• The interrupt request that has occurred has a higher interrupt level than the value set in the IL[2:0] (Interrupt
Level) bits of the PSR.
• No other interrupt request having higher priority, such as NMI, has occurred.
5.5 NMI
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece-
dence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.
5.6 Software Interrupts
The CPU provides the "int imm5" and "intl imm5, imm3" instructions allowing the software to generate any inter-
rupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction
has the operand imm3 to specify the interrupt level (0–7) to be set to the IL[2:0] bits in the PSR. The software inter-
rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation
as that of the hardware interrupt.
5.7 Interrupt Processing by the CPU
The CPU samples interrupt requests for each cycle. On accepting an interrupt request, the CPU switches to inter-
rupt processing immediately after execution of the current instruction has been completed.
Interrupt processing involves the following steps:
1. The PSR and current program counter (PC) values are saved to the stack.
2. The PSR IE bit is cleared to 0 (disabling subsequent maskable interrupts).
3. The PSR IL[2:0] bits are set to the received interrupt level. (The NMI does not affect the IL bits.)
4. The vector for the interrupt occurred is loaded to the PC to execute the interrupt handler routine.
When an interrupt is accepted, Step 2 prevents subsequent maskable interrupts. Setting the IE bit to 1 in the inter-
rupt handler routine allows handling of multiple interrupts. In this case, since the IL[2:0] bits are changed by Step 3,
only an interrupt with a higher level than that of the currently processed interrupt will be accepted.
Ending interrupt handler routines using the reti instruction returns the PSR to the state before the interrupt occurred.
The program resumes processing following the instruction being executed at the time the interrupt occurred.
Note: When HALT or SLEEP mode is canceled, the CPU jumps to the interrupt handler routine after
executing one instruction. To execute the interrupt handler routine immediately after HALT or
SLEEP mode is canceled, place the nop instruction at just behind the halt/slp instruction.
5-4
Seiko Epson Corporation
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
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