Parity Error; Overrun Error; Interrupts; Dma Transfer Requests - Epson S1C31W74 Technical Manual

13.6.2 Parity Error

If the parity function is enabled, a parity check is performed when data is received. The UART2 checks matching
between the data received in the shift register and its parity bit, and issues a parity error if the result is a non-match.
The received data that encountered an error is still transferred to the receive data buffer and the UART2_nINTF.
PEIF bit (parity error interrupt flag) is set to 1 when the data becomes ready to read from the UART2_nRXD regis-
ter (see the Note on framing error).

13.6.3 Overrun Error

If the receive data buffer is still full (two bytes of received data have not been read) when a data reception to the
shift register has completed, an overrun error occurs as the data cannot be transferred to the receive data buffer.
When an overrun error occurs, the UART2_nINTF.OEIF bit (overrun error interrupt flag) is set to 1.

13.7 Interrupts

The UART2 has a function to generate the interrupts shown in Table 13.7.1.
Interrupt
End of transmission UART2_nINTF.TENDIF When the UART2_nINTF.TBEIF bit = 1
Framing error UART2_nINTF.FEIF
Parity error UART2_nINTF.PEIF
Overrun error UART2_nINTF.OEIF
Receive buffer two UART2_nINTF.RB2FIF When the second received data byte is
bytes full
Receive buffer UART2_nINTF.RB1FIF When the first received data byte is load-
one byte full
Transmit buffer empty UART2_nINTF.TBEIF
The UART2 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.

13.8 DMA Transfer Requests

The UART2 has a function to generate DMA transfer requests from the causes shown in Table 13.8.1.
Cause to request DMA
transfer
Receive buffer Receive buffer one byte full flag
one byte full (UART2_nINTF.RB1FIF)
Transmit buffer empty Transmit buffer empty flag
(UART2_nINTF.TBEIF)
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Table 13.7.1 UART2 Interrupt Function
Interrupt flag
after the stop bit has been sent
Refer to the "Receive Errors."
Refer to the "Receive Errors."
Refer to the "Receive Errors."
loaded to the receive data buffer in which
the first byte is already received
ed to the emptied receive data buffer
When transmit data written to the trans-
mit data buffer is transferred to the shift
register
Table 13.8.1 DMA Transfer Request Causes of UART2
DMA transfer request flag
Seiko Epson Corporation
Set condition
Set condition
When the first received data
byte is loaded to the emptied
receive data buffer
When transmit data written
to the transmit data buffer is
transferred to the shift register
13 UART (UART2)
Clear condition
Writing 1 or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1 or software reset
Reading received data or
software reset
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
Clear condition
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
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