Origin Ls Detection; Ls-Z Pulse; Position Preset - Fuji Electric Faldic-a RYS-R Series User Manual

(4) Origin LS detection (40)

Because the [LS] signal requires quick response, this should be directly input to the amplifier in general. When the host controller needs the
origin signal, the origin LS detection signal can be output.
While the [LS] signal is on, the origin LS detection signal (40) is on.
SCPU32 SCPU32 SCPU32 SCPU32
APS30 APS30 APS30 APS30 SCPU32 SCPU32 SCPU32 SCPU32
ONL ONL ONL ONL
ＳＸ ＳＸ ＳＸ ＳＸ RUN RUN
RUN RUN ERR ERR
ERR ERR
TERM TERM TERM TERM TERM TERM TERM TERM
RUN RUN
SLV SLV SLV SLV RUN RUN SLV SLV SLV SLV
PWR PWR PWR PWR
ALM ALM ALM ALM
STOP STOP STOP STOP
STOP STOP BAT BAT BAT BAT STOP STOP
ALM ALM
ALM ALM
CPU CPU
CPU CPU
No. No. No. No.
LOADER LOADER LOADER LOADER LOADER LOADER LOADER LOADER

(5) LS-Z pulse

The encoder pulse count can be monitored, from the time when the [LS] signal goes to OFF level, until Z-phase signal is detected.
If this count is small, Z-phase signal of one rotation later may have been detected, depending on the origin LS response. In this case, move
the mechanical position of the origin LS.

5.4.2 Position preset

When this signal turns on, the current station number can be rewritten.
Position preset (Control input signal)
■ Function
At the ON edge(*) of this signal input, the current position can be rewritten to the value of the station mumber [PD14 to PD0].
Position preset is executable while speed zero [NZERO] signal is on.
When the position preset is executed, the origin return end is on.
This signal can reset the following alarm detection:
1) ABS (absolute) data lost
■ Parameter setting
To allocate the position preset signal to the control input terminal, set (16) to the system para.. If this signal is not allocated to the control
input terminal, this signal is deemed "always off".
Note : (*) ON edge means the control input signal's transfer point from off to on.
ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL ONL ONL ONL ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL 0 1 2 3 4 5 6 7 ONL CH1 ONL CH1 ONL CH1 ONL CH1
ONL ONL ONL ONL EMG +OT ‑OT EMG +OT ‑OT EMG +OT ‑OT EMG +OT ‑OT
RUN RUN
RUN RUN ERR ERR ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR ERR ERR ERR ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR 8 9 101112131415 ERR CH2 ERR CH2
ERR ERR ERR CH2 ERR CH2
RUN RUN
RUN RUN
ALM ALM ALM ALM
BAT BAT BAT BAT
CH CH CH CH
No. No.
No. No.
CPU CPU
CPU CPU
No. No. No. No.
PH PH PH PH
PL PL 20 20 20 20
PL PL
DA DA DA DA
1 1 1 1
B/A B/A
B/A B/A
PE1 PE1 PE1 PE1 HP2 HP2 HP2 HP2
Origin LS [LS] detection
Origin LS (origin limit switch)
5-15
FALDIC FALDIC FALDIC FALDIC FALDIC FALDIC FALDIC FALDIC
RYS201S3-VVS RYS201S3-VVS RYS201S3-VVS RYS201S3-VVS RYS201S3-VVS RYS201S3-VVS RYS201S3-VVS RYS201S3-VVS
MODE MODE MODE MODE MODE MODE MODE MODE SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT
ESC ESC ESC ESC ESC ESC ESC ESC ENT ENT ENT ENT ENT ENT ENT ENT
CHARGE CHARGE CHARGE CHARGE CHARGE CHARGE CHARGE CHARGE
K80791234 K80791234 K80791234 K80791234 K80791234 K80791234 K80791234 K80791234
L1 L1 L1 L1
L1 L1 L1 L1
L2 L2 L2 L2
L2 L2 L2 L2
L3 L3 L3 L3 L3 L3 L3 L3
DB DB DB DB DB DB DB DB
P1 P1 P1 P1 P1 P1 P1 P1
P+ P+ P+ P+ P+ P+ P+ P+
N N N N N N N N
U U U U U U U U
V V V V V V V V
W W W W W W W W
MHT260a (Engl.)