Omron C200HX Operation Manual page 81

DM (Data Memory) Area
Word(s) Bit(s)
DM 6621 00 to 07 Reserved
08 to 15 Special I/O Unit refresh (PC Link Units included)
00: Enable refresh for all Special I/O Units
01: Disable refresh for all Special I/O Units (but, not valid on Slave Racks)
A setting of 1 (Disable) is not valid for Special I/O Units mounted in Slave
Racks.
DM 6622 00 to 07 Scheduled interrupt time unit
00: 10 ms
01: 1 ms
08 to 15 Scheduled interrupt time unit enable
00: Disable (10 ms)
01: Enable setting in 00 to 07
DM 6623 00 to 15 Special I/O Unit cyclic refresh (PC Link Units included)
(Bit numbers 00 to 15 correspond to unit numbers 0 to F.)
0: Enable cyclic refresh and I/O REFRESH (IORF(97)) from main program
1: Disable (refresh only for I/O REFRESH from interrupt programs)
A setting of 01 (Disable) is valid only when the interrupt response is set to
high-speed response mode. It is not valid for normal interrupt response or for
Special I/O Units mounted in Slave Racks.
DM 6624 to 00 to 15 Reserved
DM 6644
RS-232C Port Settings (DM 6645 to DM 6649)
The following settings are accessed continually while the PC is ON.
DM 6645 00 to 03 Port settings
0: Standard (Host Link or peripheral bus serial communications mode, 1
start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps)
1: Settings in DM 6646
04 to 07 CTS control setting
0: Disable CTS control
1: Enable CTS control
08 to 11 Words linked for 1:1 PC Link
0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15
Maximum PT node number for 1:N NT Link
1 to 7 BCD (1 to 3 with a C200HE-CPUjj-E PC)
12 to 15 Serial communications mode
0: Host Link; 1: RS-232C; 2: 1:1 PC Link slave; 3: 1:1 PC Link master;
4: 1:1 NT Link; 5: 1:N NT Link
DM 6646 00 to 07 Baud rate
00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K
08 to 15 Frame format
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
10:
11:
DM 6647 00 to 15 Transmission delay
0000 to 9999: BCD in 10-ms units.
Function
Start Length
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 7 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
1 bit 8 bits
Stop Parity
1 bit Even
1 bit Odd
1 bit None
2 bit Even
2 bit Odd
2 bit None
1 bit Even
1 bit Odd
1 bit None
2 bit Even
2 bit Odd
2 bit None
Section 3-6
Default
---
Enable
10 ms
(0000)
Enable
---
Standard
Disable
LR 00 to LR 63
Host Link
1.2 K
1 start bit, 7-bit
data, 1 stop bit,
even parity
0 ms
63