IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU
will be switched off but both the high and low speed oscillators will be turned on to provide a clock
source to keep some peripheral functions operational.
IDLE2 Mode
The IDLE2 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in
the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the
CPU and low speed oscillator will be switched off but the high speed oscillator will be turned on to
provide a clock source to keep some peripheral functions operational.
Control Registers
The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the
corresponding oscillator configurations.
Register
Name
7
SCC
CKS2
HIRCC
—
HXTC
—
LXTC
—
SCC Register
Bit
7
Name
CKS2
R/W
R/W
POR
0
Bit 7~5
CKS2~CKS0: System clock selection
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from f
of the high speed system oscillator can also be chosen as the system clock source.
Bit 4
Unimplemented, read as "0"
Bit 3
FHS: High Frequency clock selection
0: HIRC
1: HXT
Bit 2
FSS: Low Frequency clock selection
0: LIRC
1: LXT
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
6
5
4
CKS1
CKS0
—
—
—
—
—
—
—
—
—
—
System Operating Mode Control Registers List
6
5
4
CKS1
CKS0
—
R/W
R/W
—
0
0
—
H
/2
H
/4
H
/8
H
/16
H
/32
H
/64
H
SUB
88
HT67F2350/HT67F2360
HT67F2370/HT67F2390
Bit
3
2
1
FHS
FSS
FHIDEN
HIRC1
HIRC0
HIRCF
—
HXTM
HXTF
—
—
LXTF
3
2
1
FHS
FSS
FHIDEN
R/W
R/W
R/W
0
0
0
or f
, a divided version
H
SUB
May 16, 2019
0
FSIDEN
HIRCEN
HXTEN
LXTEN
0
FSIDEN
R/W
0
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