Holtek HT67F2350 Manual page 141

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
Bit 2 STnPOL: STMn STPn Output polarity control
0: Non-inverted
1: Inverted
This bit controls the polarity of the STPn output pin. When the bit is set high the
STMn output pin will be inverted and not inverted when the bit is zero. It has no effect
if the STMn is in the Timer/Counter Mode.
STnDPX: STMn PWM duty/period control
Bit 1
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0 STnCCLR: STMn Counter Clear condition selection
0: Comparator P match
1: Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the STnCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The STnCCLR bit is not
used in the PWM Output, Single Pulse Output or Capture Input Mode.
STMnRP Register
Bit 7
Name STnRP7
R/W R/W
POR 0
STnRP7~STnRP0: STMn CCRP 8-bit register, compared with the STMn counter bit 15~bit 8
Bit 7~0
Comparator P match period =
0: 65536 STMn clocks
1~255: (1~255) × 256 STMn clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter's highest eight bits. The result of this
comparison can be selected to clear the internal counter if the STnCCLR bit is set to
zero. Setting the STnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.60
6 5 4
STnRP6 STnRP5 STnRP4
R/W R/W R/W
0 0 0
141
3 2 1
STnRP3 STnRP2 STnRP1
R/W R/W R/W
0 0 0
May 16, 2019
0
STnRP0
R/W
0