Holtek HT67F2350 Manual page 145

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
Timer/Counter Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
STMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STMn output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register should be set to 10 respectively
and also the STnIO1 and STnIO0 bits should be set to 10 respectively. The PWM function within
the STMn is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the STnCCLR bit has no effect as the PWM
period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the STnDPX bit in the STMnC1 register. The PWM waveform frequency and
duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM Output mode, the STnCCLR bit has no effect as the
PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the STnDPX bit in the STMnC1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
• 16-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=0
If f =16MHz, STMn clock source is f
SYS
The STMn PWM output frequency=(f
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=1
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is
equal to 0.
Rev. 1.60
CCRP 1~255
Period CCRP × 256
Duty CCRA
/4, CCRP=2 and CCRA=128,
SYS
/4) / (2×256)=f /2048=8 kHz, duty=128/(2×256)= 25%.
SYS SYS
CCRP 1~255
Period CCRA
Duty CCRP × 256
145
0
65536
0
65536
May 16, 2019