HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
EEC Register
Bit
7
Name
—
R/W
—
POR
—
Bit 7~4
Unimplemented, read as "0"
Bit 3
WREN: Data EEPROM write enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations. Note that the WREN bit will automatically be cleared to
zero after the write operation is finished.
Bit 2
WR: EEPROM write control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM read enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0
RD: EEPROM read control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The
WR and RD can not be set to "1" at the same time.
Reading Data from the EEPROM
To read data from the EEPROM, the EEPROM address of the data to be read must first be placed in
the EEA register or EEAL/EEAH register pair. Then the read enable bit, RDEN, in the EEC register
must be set high to enable the read function. If the RD bit in the EEC register is now set high, a
read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit
has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero,
after which the data can be read from the EED register. The data will remain in the EED register
until another read or write operation is executed. The application program can poll the RD bit to
determine when the data is valid for reading.
Rev. 1.60
6
5
4
—
—
—
WREN
—
—
—
—
—
—
79
3
2
1
WR
RDEN
R/W
R/W
R/W
0
0
0
May 16, 2019
0
RD
R/W
0
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