Holtek HT67F2350 Manual page 162

Counter Value
CCRP
CCRA
PTnON
PTnPAU
PTnPOL
CCRA Int. Flag
PTMnAF
CCRP Int. Flag
PTMnPF
PTMn O/P Pin
(PTnOC=1)
PTMn O/P Pin
(PTnOC=0)
PWM Duty Cycle
set by CCRA
Note: 1. The counter is cleared by CCRP.
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTnIO [1:0]=00 or 01
4. The PTnCCLR bit has no influence on PWM operation
5. n=0, 1, 4, 5, 6 or 7 for 10-bit PTM while n=2 or 3 for 16-bit PTM
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
Counter cleared by
CCRP
Pause
PWM Period set by CCRP
PWM Output Mode
162
HT67F2350/HT67F2360
HT67F2370/HT67F2390
PTnM [1:0] = 10
Counter Reset when
PTnON returns high
Counter Stop if
Resume
PTnON bit low
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
When PTnPOL = 1
May 16, 2019
Time