Managing Receiver Errors - Holtek HT67F2350 Manual

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
Receiving Break
Any break character received by the UARTn will be managed as a framing error. The receiver
will count and expect a certain number of bit times as specified by the values programmed into
the BNOn and STOPSn bits. If the break is much longer than 13 bit times, the reception will be
considered as complete after the number of bit times specified by BNOn and STOPSn. The RXIFn
bit is set, FERRn is set, zeros are loaded into the receive data register, interrupts are generated if
appropriate and the RIDLEn bit is set. A break is regarded as a character that contains only zeros
with the FERRn flag being set. If a long break signal has been detected, the receiver will regard it as
a data frame including a start bit, data bits and the invalid stop bit and the FERRn flag will be set.
The receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not
make the assumption that the break condition on the line is the next start bit. The break character
will be loaded into the buffer and no further data will be received until stop bits are received. It
should be noted that the RIDLEn read only flag will go high when the stop bits have not yet been
received. The reception of a break character on the UARTn registers will result in the following:
• The framing error flag, FERRn, will be set.
• The receive data register, TXR_RXRn, will be cleared.
• The OERRn, NFn, PERRn, RIDLEn or RXIFn flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit
and the reading of a stop bit, the receiver status flag in the UnSR register, otherwise known as the
RIDLEn flag, will have a zero value. In between the reception of a stop bit and the detection of
the next start bit, the RIDLEn flag will have a high value, which indicates the receiver is in an idle
condition.
Receiver Interrupt
The read only receive interrupt flag, RXIFn, in the UnSR register is set by an edge generated by the
receiver. An interrupt is generated if RIEn=1, when a word is transferred from the Receive Shift
Register, RSRn, to the Receive Data Register, TXR_RXRn. An overrun error can also generate an
interrupt if RIEn=1.

Managing Receiver Errors

Several types of reception errors can occur within the UARTn module, the following section
describes the various types and how they are managed by the UARTn.
Overrun Error – OERRn
The TXR_RXRn register is composed of a two byte deep FIFO data buffer, where two bytes can be
held in the FIFO register, while a 3
entirely shifted in, the data should be read from the TXR_RXRn register. If this is not done, the
overrun error flag OERRn will be consequently indicated.
In the event of an overrun error occurring, the following will happen:
• The OERRn flag in the UnSR register will be set.
• The TXR_RXRn contents will not be lost.
• The shift register will be overwritten.
• An interrupt will be generated if the RIEn bit is set.
The OERRn flag can be cleared by an access to the UnSR register followed by a read to the TXR_
RXRn register.
Rev. 1.60
byte can continue to be received. Before the 3
th
215
byte has been
th
May 16, 2019