Control Registers - Holtek BS86DH12C Manual

BS86DH12C
High Voltage Touch A/D Flash MCU with HVIO
IDLE2 Mode
The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU
will be switched off but the high speed oscillator will be on to provide a clock source to keep some
peripheral functions operational.

Control Registers

The registers, SCC, HIRCC and LXTC, are used to control the system clock and the corresponding
oscillator configurations.
Register
Name
7
SCC CKS2
HIRCC —
LXTC —
• SCC Register
Bit 7
Name CKS2
R/W R/W
POR 0
CKS2~CKS0: System clock selection
Bit 7~5
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from f
of the high speed system oscillator can also be chosen as the system clock source.
Bit 4~3 Unimplemented, read as "0"
Bit 2 FSS: Low frequency clock selection
0: LIRC
1: LXT
Bit 1 FHIDEN: High frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the high speed oscillator is activated or stopped
when the CPU is switched off by executing an "HALT" instruction.
Bit 0 FSIDEN: Low frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the low speed oscillator is activated or stopped
when the CPU is switched off by executing an "HALT" instruction.
Rev. 1.00
6 5 4
CKS1 CKS0 —
— — —
— — —
System Operating Mode Control Register List
6 5 4
CKS1 CKS0 —
R/W R/W —
0 0 —
H
/2
H
/4
H
/8
H
/16
H
/32
H
/64
H
SUB
47
Bit
3 2 1
— FSS FHIDEN
HIRC1 HIRC0 HIRCF
— LXTSP LXTF
3 2 1
— FSS FHIDEN
— R/W R/W
— 0 0
or f , a divided version
H SUB
October 26, 2018
0
FSIDEN
HIRCEN
LXTEN
0
FSIDEN
R/W
0