Uart Interrupt Structure - Holtek HT67F2350 Manual

Noise Error – NFn
Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is
detected within a frame, the following will occur:
• The read only noise flag, NFn, in the UnSR register will be set on the rising edge of the RXIFn
bit.
• Data will be transferred from the shift register to the TXR_RXRn register.
• No interrupt will be generated. However this bit rises at the same time as the RXIFn bit which
itself generates an interrupt.
Note that the NFn flag is reset by an UnSR register read operation followed by a TXR_RXRn
register read operation.
Framing Error – FERRn
The read only framing error flag, FERRn, in the UnSR register, is set if a zero is detected instead of
stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERRn flag will be
set. The FERRn flag and the received data will be recorded in the UnSR and TXR_RXRn registers
respectively and the FERRn flag will be cleared in any reset.
Parity Error – PERRn
The read only parity error flag, PERRn, in the UnSR register, is set if the parity of the received
word is incorrect. This error flag is only applicable if the parity function is enabled, PRENn=1, and
if the parity type, odd or even, is selected. The read only PERRn flag and the received data will be
recorded in the UnSR and TXR_RXRn registers respectively and the flag will be cleared on any
reset. It should be noted that the FERRn and PERRn flags in the UnSR register should first be read
by the application programs before reading the data word.

UART Interrupt Structure

Several individual UARTn conditions can generate a UARTn interrupt. When these conditions
exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are
a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address
detect and an RXn pin wake-up. When any of these conditions are created, if its corresponding
interrupt control is enabled and the stack is not full, the program will jump to its corresponding
interrupt vector where it can be serviced before returning to the main program. Four of these
conditions have the corresponding UnSR register flags which will generate a UARTn interrupt if
its associated interrupt enable control bit in the UnCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable control bits, while the two receiver interrupt
conditions have a shared enable control bit. These enable bits can be used to mask out individual
UARTn interrupt sources.
The address detect condition, which is also a UARTn interrupt source, does not have an associated
flag, but will generate a UARTn interrupt when an address detect condition occurs if its function is
enabled by setting the ADDENn bit in the UnCR2 register. An RXn pin wake-up, which is also a
UARTn interrupt source, does not have an associated flag, but will generate a UARTn interrupt if the
UARTn clock source, f
set when a falling edge on the RXn pin occurs. Note that in the event of an RXn wake-up interrupt
occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for
the oscillator to restart and stabilize before the system resumes normal operation.
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
, is switched off and the WAKEn and RIEn bits in the UnCR2 register are
H
216
HT67F2350/HT67F2360
HT67F2370/HT67F2390
May 16, 2019