Uart Setup And Control - Holtek HT67F2350 Manual

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
BRGn Register
Bit 7
Name D7
R/W R/W
POR x
Bit 7~0 D7~D0: Baud Rate values
By programming the BRGHn bit in the UnCR2 register which allows selection of the
related formula described above and programming the required value in the BRGn
register, the required baud rate can be setup.
Calculating the Baud Rate and Error Values
For a clock frequency of 4MHz, and with BRGHn set to 0 determine the BRGn register value N, the
actual baud rate and the error value for a desired baud rate of 4800.
From the above table the desired baud rate BR=f
Re-arranging this equation gives N=[f
Giving a value for N=[4000000 / (4800×64)] - 1=12.0208
To obtain the closest value, a decimal value of 12 should be placed into the BRGn register. This
gives an actual or calculated baud rate value of BR=4000000 / [64 × (12+1)]=4808
Therefore the error is equal to (4808 - 4800) / 4800=0.16%

UART Setup and Control

For data transfer, the UARTn function utilizes a non-return-to-zero, more commonly known as
NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits.
Parity is supported by the UARTn hardware and can be setup to be even, odd or no parity. For the
most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1,
is used as the default setting, which is the setting at power-on. The number of data bits and stop
bits, along with the parity, are setup by programming the corresponding BNOn, PRTn, PRENn and
STOPSn bits in the UnCR1 register. The baud rate used to transmit and receive data is setup using
the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although
the transmitter and receiver of the UARTn are functionally independent, they both use the same data
format and baud rate. In all cases stop bits will be used for data transmission.
Enabling/Disabling the UART Interface
The basic on/off function of the internal UARTn function is controlled using the UARTENn bit in
the UnCR1 register. If the UARTENn, TXENn and RXENn bits are set, then these two UARTn pins
will act as normal TXn output pin and RXn input pin respectively. If no data is being transmitted on
the TXn pin, then it will default to a logic high value.
Clearing the UARTENn bit will disable the TXn and RXn pins and then these two pins can be used
as an I/O or other pin-shared functional pins by properly configurations. When the UARTn function
is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining
residual data. Disabling the UARTn will also reset the enable control, the error and status flags with
bits TXENn, RXENn, TXBRKn, RXIFn, OERRn, FERRn, PERRn and NFn being cleared while
bits TIDLEn, TXIFn and RIDLEn will be set. The remaining control bits in the UnCR1, UnCR2 and
BRGn registers will remain unaffected. If the UARTENn bit in the UnCR1 register is cleared while
the UARTn is active, then all pending transmissions and receptions will be immediately suspended
and the UARTn will be reset to a condition as defined above. If the UARTn is then subsequently re-
enabled, it will restart again in the same configuration.
Rev. 1.60
6 5 4
D6 D5 D4
R/W R/W R/W
x x x
/ [64 (N+1)]
H
/ (BR×64)] - 1
H
211
3 2 1
D3 D2 D1
R/W R/W R/W
x x x
"x": unknown
May 16, 2019
0
D0
R/W
x