Holtek HT67F2350 Manual page 139

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
STMnC0 Register
Bit 7
Name STnPAU
R/W R/W
POR 0
Bit 7 STnPAU: STMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STMn will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4 STnCK2~STnCK0: Select STMn Counter clock
000: f
001: f
010: f
011: f
100: f
101: f
110: STCKn rising edge clock
111: STCKn falling edge clock
These three bits are used to select the clock source for the STMn. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
f
SYS
can be found in the oscillator section.
Bit 3 STnON: STMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the STMn. Setting the bit high enables
the counter to run while clearing the bit disables the STMn. Clearing this bit to zero
will stop the counter from counting and turn off the STMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value will
be reset to zero, however when the bit changes from high to low, the internal counter will
retain its residual value until the bit returns high again. If the STMn is in the Compare
Match Output Mode then the STMn output pin will be reset to its initial condition, as
specified by the STnOC bit, when the STnON bit changes from low to high.
Bit 2~0 Unimplemented, read as "0"
STMnC1 Register
Bit 7
Name STnM1
R/W R/W
POR 0
Bit 7~6 STnM1~STnM0: Select STMn Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Output Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STMn. To ensure reliable
operation the STMn should be switched off before any changes are made to the
STnM1 and STnM0 bits. In the Timer/Counter Mode, the STMn output pin control
will be disabled.
Rev. 1.60
6 5
STnCK2 STnCK1 STnCK0
R/W R/W R/W
0 0
/4
SYS
SYS
/16
H
/64
H
SUB
SUB
is the system clock, while f and f
H
6 5 4
STnM0 STnIO1 STnIO0
R/W R/W R/W
0 0 0
139
4 3 2
STnON —
R/W —
0 0 —
are other internal clocks, the details of which
SUB
3 2
STnOC STnPOL STnDPX
R/W R/W R/W
0 0
1 0
— —
— —
— —
1 0
STnCCLR
R/W
0 0
May 16, 2019