Standard Type Tm Operation Modes - Holtek HT67F2350 Manual

Standard Type TM Operation Modes

The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the STnM1 and STnM0 bits in the STMnC1 register.
Compare Match Output Mode
To select this mode, bits STnM1 and STnM0 in the STMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the STnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both STMnAF and STMnPF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the STnCCLR bit in the STMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMnAF interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when STnCCLR is high no STMnPF interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA can not be set to "0".
As the name of the mode suggests, after a comparison is made, the STMn output pin, will change
state. The STMn output pin condition however only changes state when a STMnAF interrupt request
flag is generated after a compare match occurs from Comparator A. The STMnPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STMn
output pin. The way in which the STMn output pin changes state are determined by the condition of
the STnIO1 and STnIO0 bits in the STMnC1 register. The STMn output pin can be selected using
the STnIO1 and STnIO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the STMn output pin, which is
setup after the STnON bit changes from low to high, is setup using the STnOC bit. Note that if the
STnIO1 and STnIO0 bits are zero then no pin change will take place.
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
142
HT67F2350/HT67F2360
HT67F2370/HT67F2390
May 16, 2019