Holtek TinyPower HT69F40A Manual

Tinypower i/o flash 8-bit mcu with lcd & eeprom

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TinyPower

I/O Flash 8-Bit MCU with LCD & EEPROM

HT69F30A/HT69F40A/HT69F50A

Revision: V1.20

Date: ��to�e� 0�� 201�

��to�e� 0�� 201�

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Summary of Contents for Holtek TinyPower HT69F40A

Page 1: P�Og�Amming Conside�Ations
TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM HT69F30A/HT69F40A/HT69F50A Revision: V1.20 Date: ��to�e� 0�� 201� ��to�e� 0�� 201�...
Page 2: Table Of Contents
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Table of Contents Features ......................6 CPU Featu�es ......................... 6 Pe�iphe�al Featu�es ......................... 6 General Description ..................7 Selection Table ....................7 Block Diagram ....................8 Pin Assignment ....................9 Pin Description ....................
Page 3: Exte�Nal C�Ystal/Ce�Ami
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM EEPROM Data Memory .................. 48 EEPR�M Registe�s ......................4� Reading Data f�om the EEPR�M ..................�0 W�iting Data to the EEPR�M ....................�0 W�ite P�ote�tion ........................�0 EEPR�M Inte��upt ........................ �0 P�og�amming Conside�ations ....................
Page 4: Exte�Nal Rc �S�Illato� - Erc
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Input/Output Ports ..................78 I/� Po�t Registe� List ......................7� Pull-high Resisto�s ........................ �1 Po�t A Wake-up ........................�1 I/� Po�t Cont�ol Registe�s ..................... �1 Pin-sha�ed Fun�tions ......................�1 I/� Pin St�u�tu�es ........................92 P�og�amming Conside�ations ....................
Page 5 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Interrupts ...................... 158 Inte��upt Registe�s ....................... 1�� Inte��upt �pe�ation ......................164 Exte�nal Inte��upt ......................... 166 Multi-fun�tion Inte��upt ......................166 Time Base Inte��upt ......................167 EEPR�M Inte��upt ......................16� LVD Inte��upt ........................16� TM Inte��upts ........................
Page 6: Features
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Features CPU Features • Operating voltage =4MHz: 2.2V~5.5V ♦ =8MHz: 2.4V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =20MHz: 4.5V~5.5V ♦ • Up to 0.2μs instruction cycle with 20MHz system clock at V • Power down and wake-up functions to reduce power consumption • Oscillator types External Crystal – HXT ♦ External 32.765kHz Crystal – LXT ♦ External RC – ERC ♦ External Clock – EC ♦ Internal RC – HIRC ♦ Internal 32kHz RC – LIRC ♦...
Page 7: General Description
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM General Description The HT69Fx0A series of devices are Flash Memory LCD type 8-bit high performance RISC architecture microcontrollers, designed for applications which require an LCD interface. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory. Analog features include multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments.
Page 8: Block Diagram
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Block Diagram Watchdog Voltage Timer Detect Reset Circuit Voltage Reset 8-bit Interrupt RISC Controller Core Stack Flash/EEPROM ERC/EC/HXT Programming Oscillator Circuitry (ICP)/OCDS HIRC LIRC/LXT Flash EEPROM Time Oscillator Oscillator Program Data Data Base...
Page 9: Pin Assignment
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pin Assignment 48 47 46 45 44 43 42 41 40 39 38 37 PB3/XT2 PA7/RES VLCD PD0/SEG0/INT1 VMAX PD1/SEG1/TCK0 PD2/SEG2/TCK1 PC0/V2 PD3/SEG3 PC1/C1 HT69F30A PD4/SEG4 PC2/C2 PD5/SEG5 48 LQFP-A COM0 PD6/SEG6 COM1...
Page 10 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PB3/XT2 PA7/RES VLCD PD0/SEG0/INT1 VMAX PD1/SEG1/TCK0 PD2/SEG2/TCK2 PC0/V2 PD3/SEG3/TCK1 PC1/C1 PD4/SEG4/TP1A PC2/C2 PD5/SEG5/TP1B_0 PD6/SEG6/TP1B_1 COM0 HT69F40A COM1 PD7/SEG7/TP1B_2 64 LQFP-A COM2 PE0/SEG8 COM3/SEG36 PE1/SEG9 SEG35 PE2/SEG10 SEG34 PE3/SEG11 SEG33 PE4/SEG12 SEG32 PE5/SEG13 PG7/SEG31...
Page 11 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PA7/RES PB3/XT2 PD0/SEG0/INT1 PLCD PD1/SEG1/TCK0 VMAX PD2/SEG2/TCK2 PD3/SEG3/TCK1 PC0/V2 PD4/SEG4/TP1A PC1/C1 PD5/SEG5/TP1B_0 PC2/C2 PD6/SEG6/TP1B_1 COM0 HT69F50A PD7/SEG7/TP1B_2 COM1 64 LQFP-A PE0/SEG8 COM2 PE1/SEG9 COM3/SEG36 PE2/SEG10 PH3/SEG35 PE3/SEG11 PH2/SEG34 PE4/SEG12 PH1/SEG33 PE5/SEG13 PH0/SEG32 PE6/SEG14...
Page 12 SEG42 PE7/SEG15 SEG41 PF0/SEG16 SEG40 PF1/SEG17 PH7/SEG39 PF2/SEG18 21 22 23 24 25 26 27 28 29 30 31 32 33 3435 36 3738 39 40 HT69V50A 80 LQFP- A Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, the output function is determined by the corresponding software control bits except the functions determined by the configuration options. 2. The HT69V50A device is the EV chip of the HT69Fx0A series of devices. It supports the “On-Chip Debug” function for debugging during development using the OCDSDA and OCDSCK pins connected to the Holtek HT-IDE development tools. Rev. 1.20 ��to�e� 0�� 201�...
Page 13: Pin Description
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pin Description HT69F30A Pad Name Function Description PAWU PAPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up and wake-up PAFS INTEG PA0/INT1/ICPDA/ INT1 INTC0 — Exte�nal Inte��upt 1 �CDSDA ICPDA — CM�S ICP Data/Add�ess �CDSDA —...
Page 14 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PCPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PCFS PC0/V2 PCFS — A� LCD voltage pump PCPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PCFS PC1/C1 PCFS —...
Page 15 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PEPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PEFS PE4/SEG12 SEG12 PEFS — A� LCD segment output PEPU PE� CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PEFS PE�/SEG13 SEG13...
Page 16 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM HT69F40A Pad Name Function Description PAWU PAPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up and wake-up PAFS INTEG PA0/INT1/TCK1/ INT1 INTC0 — Exte�nal Inte��upt 1 ICPDA/�CDSDA TCK1 — TM1 input ICPDA —...
Page 17 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PBPU PB� CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PBFS PB�/TP1B_0 TP1B_0 PBFS CM�S TM1 I/� pin PBPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PBFS PB6/TP1B_1 TP1B_1 PBFS...
Page 18 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PDPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PDFS PD6/SEG6/ PDFS SEG6 — A� LCD segment output TP1B_1 PDFS TP1B_1 CM�S TM1 I/� pin PDPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PDFS PD7/SEG7/ PDFS...
Page 19 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PFPU PF� CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PFFS PF�/SEG21 SEG21 PFFS — A� LCD segment output PFPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PFFS PF6/SEG22 SEG22...
Page 20 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM HT69F50A Pad Name Function Description PAWU PAPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up and wake-up PAFS INTEG PA0/INT1/TCK1/ INT1 INTC0 — Exte�nal Inte��upt 1 ICPDA/�CDSDA TCK1 — TM1 input ICPDA —...
Page 21 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PBPU PB� CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PBFS PB�/TP1B_0 TP1B_0 PBFS CM�S TM1 I/� pin PBPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PBFS PB6/TP1B_1 TP1B_1 PBFS...
Page 22 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PDPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PDFS PD6/SEG6/ PDFS SEG6 — A� LCD segment output TP1B_1 PDFS TP1B_1 CM�S TM1 I/� pin PDPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PDFS PD7/SEG7/ PDFS...
Page 23 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PFPU PF� CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PFFS PF�/SEG21 SEG21 PFFS — A� LCD segment output PFPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PFFS PF6/SEG22 SEG22...
Page 24: Absolute Maximum Ratings
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pad Name Function Description PHPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PHFS PH6/SEG3� SEG3� PHFS — A� LCD segment output PHPU CM�S Gene�al pu�pose I/�. Registe� ena�led pull-up PHFS PH7/SEG39 SEG39 PHFS...
Page 25: D.c. Characteristics
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM D.C. Characteristics Ta=2�°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions =4MHz — �.� =�MHz — �.� �pe�ating Voltage (HXT) — =12MHz — �.� =16MHz 4.� — �.� =4MHz —...
Page 26 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — �00 7�0 μA No load� f =�MHz� f /2� WDT ena�le �V — �00 1200 μA — μA No load� f =�MHz�...
Page 27 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions 3V No load� system HALT� WDT ena�le� — 1.� μA Stand�y Cu��ent (Idle0.) STB4 (HIRC� f =off� f =3276�Hz� LXTLP=1 LIRC �V —...
Page 28: A.c. Characteristics
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM A.C. Characteristics Ta=2�°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Condition 2.2~�.�V — 2.4~�.�V — � �pe�ating Clo�k — 2.7~�.�V — 4.�~�.�V — 2.2V~�.�V — 2.2V~�.�V — � System �lo�k (HXT) —...
Page 29: Lvd & Lvr Electrical Characteristics
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Condition System Reset Delay Time (Powe� �n Reset� LVR �eset� — — 2� �0 LVR S/W �eset (LVRC)� WDT S/W �eset (WDTC)) RSTD System Reset Delay Time —...
Page 30: Lcd D.c. Characteristics
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LCD D.C. Characteristics Ta=2�°C Test Condition Symbol Parameter Min. Typ. Max. Unit Condition Stand�y Cu��ent (Sleep) — μA No load� system HALT� LCD on� � f off� STB1 WDT off� C type� V �...
Page 31: Power-On Reset Characteristics
V D D P O R T i m e System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set...
Page 32: P�Og�Am Counte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM S Y S ( S y s t e m C l o c k ) P h a s e C l o c k T 1 P h a s e C l o c k T 2 P h a s e C l o c k T 3 P h a s e C l o c k T 4 P r o g r a m...
Page 33: Sta�K
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P r o g r a m C o u n t e r T o p o f S t a c k S t a c k L e v e l 1 S t a c k L e v e l 2 S t a c k...
Page 34: Flash Program Memory
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of up to 8k×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries information. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Device Capacity HT69F30A 2K×16...
Page 35: Look-Up Ta�Le
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRDC [m]” or “TABRDL [m]” instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte...
Page 36: In Ci
In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA P�og�amming Se�ial Data ICPCK P�og�amming Clo�k Powe� Supply G�ound The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data...
Page 37: N-Chip De�Ug Suppo�T - �Cds
HT69V50A EV chip for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the HT69Fx0A series of devices will have no effect in the HT69V50A EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description �CDSDA �CDSDA �n-Chip De�ug Suppo�t Data/Add�ess input/output �CDSCK...
Page 38: Data Memory
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into three sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The third area is reserved for the LCD Memory. This special area of Data Memory is mapped directly to the LCD display so data written into this memory area will directly affect the displayed data. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. Structure The Data Memory is subdivided into several banks, all of which are implemented in 8-bit wide RAM. The Data Memory located in Bank 0 is subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the Data Memory for all devices is the address 00H. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. The LCD Memory is mapped into Bank 1. The Banks 2 to 3 contain only General Purpose Data Memory for those devices with larger Data Memory capacities. As the Special Purpose Data Memory...
Page 39: Gene�Al Pu�Pose Data Memo�Y
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Bank 0 Spe�ial Pu�pose Data Memo�y 40H in Bank 1 LCD Memo�y in Bank 1 �0H Gene�al Pu�pose Data Memo�y Bank 0 Bank 2 Bank 3 Data Memory Structure General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading...
Page 40 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Bank 0� 1 Bank 0 Bank 1 IAR0 IAR1 0�H Unused TBLP 0�H TBLH 4�H TM1C0 TBHP TM1C1 STATUS TM1DL SM�D TM1DH TM1AL LVDC INTEG TM1AH WDTC INTC0 Unused INTC1 SM�D1 LVRC �FH...
Page 41 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Bank 0� 1� 2 Bank 0� 2 Bank 1 IAR0 IAR1 0�H Unused TBLP 0�H TBLH 4�H TM1C0 TBHP TM1C1 STATUS TM1C2 SM�D TM1DL LVDC TM1DH INTEG TM1AL WDTC TM1AH TM1BL INTC0 �0H...
Page 42 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Bank 0� 1� 2� 3 Bank 0� 2� 3 Bank 1 IAR0 IAR1 0�H Unused TBLP 0�H TBLH 4�H TM1C0 TBHP TM1C1 STATUS TM1C2 SM�D TM1DL LVDC TM1DH INTEG TM1AL WDTC TM1AH TM1BL...
Page 43: Special Function Register Description
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation.
Page 44: Bank Pointe� - Bp
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Bank Pointer – BP Depending upon which device is used, the Data Memory is divided into several banks. Selecting the required Data Memory area is achieved using the Bank Pointer. Bits 0~1 of the Bank Pointer are used to select Data Memory Banks 0~3. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. Device HT69F30A — — — — — — — DMBP0 HT69F40A — — — — —...
Page 45 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • HT69F50A Name — — — — — — DMBP1 DMBP0 — — — — — — P�R — — — — — — Bit 7~2 Unimplemented, read as "0" Bit 1~0 DMBP1, DMBP0: Data memory bank point 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3...
Page 46 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out.
Page 47 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM STATUS Register Name — — T� �V — — P�R — — “x” unknown Bit 7, 6 Unimplemented, read as “0” Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero...
Page 48: Eeprom Data Memory
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM EEPROM Data Memory The EEPROM Data Memory capacity is up to 128×8 bits for this series of devices. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read andWrite operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device Capacity Address HT69F30A 64×� 00H~3FH HT69F40A 12�×� 00H~7FH HT69F�0A 12�×� 00H~7FH EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Register List •...
Page 49 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • HT69F40A/HT69F50A Name — EEA6 EEA� EEA4 EEA3 EEA2 EEA1 EEA0 — P�R — “x”: unknown Bit 7 Unimplemented, read as "0" EEA6~EEA0: Data EEPROM address bit 6~bit 0 Bit 6~0 EED Register Name EED� EED4 EED� EED4 EED3 EED2 EED1 EED0 P�R “x”: unknown...
Page 50: Reading Data F�Om The Eepr
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEAregister. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended.
Page 51 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Programming Examples Reading Data from the EEPROM – Polling Mothod MOV A, EEPROM_ADRES ; user defined address MOV EEA, A...
Page 52: Oscillator
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external...
Page 53 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM High Speed �s�illation (H�SC) Fast Wake-up f�om SLEEP Mode o� IDLE Mode Cont�ol (fo� HXT only) /� P�es�ale� HIRC High Speed �s�illation Configu�ation �ption CKS[2:0]� HLCLK Low Speed �s�illation (L�SC) TBCK LIRC Time Base...
Page 54 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz �MHz 4MHz 1MHz 100pF 100pF 4��kHz (see Note2) 100pF 100pF Note: 1. C1 and C2 values a�e fo� guidan�e only. 2. XTAL mode configuration option: 455kHz. Crystal Recommended Capacitor Values External RC Oscillator –...
Page 55 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. The external parallel feedback resistor, Rp, is required. Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with inter connecting lines are all located as close to the MCU as possible.
Page 56 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP Bit LXT Mode Qui�k Sta�t Low-powe� After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Low-power mode. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during...
Page 57: Operating Modes And System Clocks
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clock The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, f , or low frequency, f , source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from an HXT, ERC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from the clock, f . If f is selected then it can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of /2~f /64. The f clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.
Page 58: System �Pe�Ation Modes
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to...
Page 59 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the SMOD1 register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f , will also be Control Register A register pair, SMOD and SMOD1, is used for overall control of the internal clocks within the device. SMOD Register Name CKS2 CKS1 CKS0 FSTEN LT� HT� IDLEN HLCLK P�R CKS2~CKS0: The system clock selection when HLCLK is "0" Bit 7~5 000: f or f LIRC 001: f or f LIRC...
Page 60 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM HTO: High speed system oscillator ready flag Bit 2 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used. bit 1 IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. bit 0 HLCLK: System clock selection 0: f /2~f /64 or f 1: f This bit is used to select if the f clock or the f /2~f /64 or f...
Page 61: Fast Wake-Up
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows f , namely the LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is f , the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the FastWake-up function has no effect because the f clock is stopped. The FastWake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock and if the Fast Wake-up function is enabled, then it will take one to two t clock cycles of the LIRC oscillator for the system to wake-up. The system will then initially run under the f clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC/HIRC or EC/LIRC oscillator is used as the system oscillator, then it will take15~16 clock cycles of the ERC/HIRC oscillator or 1~2 clock cycles of the LIRC osrillator respectively to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Wake-up Time Wake-up Time Wake-up Time Wake-up Time...
Page 62: Pe�Ating Mode Swit�Hing And Wake-Up
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, f , to the clock source, f /2~f /64 or f . If the clock is from the f , the high speed clock source will stop running to conserve power. When this happens it must be noted that the f /16 and f /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the LCD driver. The accompanying flowchart shows what happens when the device moves between the various operating modes. I D L E 1 N O R M A L H A L T i n s t r u c t i o n i s e x e c u t e d / 6 4 S Y S C P U s t o p...
Page 63: N�Rmal Mode To Sl�W Mode Swit�Hing
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. N O R M A L M o d e C K S 2 ~ C K S 0 = 0 0 x B & H L C L K = 0 S L O W M o d e...
Page 64: Sl�W Mode To N�Rmal Mode Swit�Hing
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM S L O W M o d e C K S 2 ~ C K S 0 ¹ 0 0 0 B , 0 0 1 B a s H L C L K = 0 o r H L C L K = 1 N O R M A L M o d e W D T a n d L V D a r e a l l o f f...
Page 65: Ente�Ing The Sleep0 Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and the f clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped as the WDT is disabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT”...
Page 66: Ente�Ing The Idle1 Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in SMOD1 register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and f clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting as the WDT clock source is derived from the f clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption.
Page 67: Wake-Up
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Page 68: Watchdog Timer
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock f , which is in turn supplied by the f clock. The f clock can be sourced from either the LXT or LIRC oscillator selected by a configuration option. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with V , temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required time-out period as well as the enable/disable operation. This register controls the overall operation of the Watchdog Timer.
Page 69: Wat�Hdog Time
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM SMOD1 Register Name FSYS�N — — — — LVRF — — — — P�R — — — — “x” unknown Bit 7 FSYSON: f Control in IDLE Mode Described elsewhere. Bit 6~3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag Described elsewhere. Bit 1 LRF: LVR Control register software reset flag Described elsewhere.
Page 70: Reset And Initialisation
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT contents. The maximum time out period is when the 2 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 division ratio, and a minimum timeout of 7.8ms for the 2 division ration. WDTC Registe� WE4~WE0 �its Reset MCU “CLR WDT”Inst�u�tion � �-stage Divide� WDT P�es�ale� LIRC Low Speed �s�illato� WS2~WS0 �-to-1 MUX WDT Time-out...
Page 71: Reset Fun�Tions
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Reset Functions There are five ways in which a reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. V D D 0 .
Page 72 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. 0 . 9 V 0 . 4 V R E S R S T D + S S T I n t e r n a l R e s e t...
Page 73 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • LVRC Register Name LVS7 LVS6 LVS� LVS4 LVS3 LVS2 LVS1 LVS0 P�R Bit 7~0 LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Any other values: Generates MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 f clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined register values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 f clock cycles. However in this situation the register contents will be reset to the POR value. • SMOD1 Register Name FSYS�N —...
Page 74: Reset Initial Conditions
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for details. W D T T i m e - o u t S S T I n t e r n a l R e s e t WDT Time-out Reset during SLEEP or IDLE Timing Chart Note: The t is 15~16 clock cycles if the system clock source is provided by ERC or...
Page 75 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Register Reset Status Table WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) IAR0 ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u...
Page 76 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) ● ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u u ●...
Page 77 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) TM1C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TM1DL...
Page 78: Input/Output Ports
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PH. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Port Register List HT69F30A Register Name PAWU PAWU7 PAWU6 PAWU� PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU�...
Page 79 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM HT69F40A Register Name PAWU PAWU7 PAWU6 PAWU� PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU� PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA� PAC7 PAC6 PAC� PAC4 PAC3 PAC2 PAC1 PAC0 PBPU PBPU7 PBPU6...
Page 80 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM HT69F50A Register Name PAWU PAWU7 PAWU6 PAWU� PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU� PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA� PAC7 PAC6 PAC� PAC4 PAC3 PAC2 PAC1 PAC0 PBPU PBPU7 PBPU6...
Page 81: Pull-High Resisto
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PHPU, and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. I/O Port Control Registers Each Port has its own control register, known as PAC~PHC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state...
Page 82 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Pin-shared Function Selection Register List • HT69F30A Register Name PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 — PCFS — — — — — PCFS2 PCFS1 PCFS0 PDFS PDFS7 PDFS6 PDFS�...
Page 83 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PAFS Register – HT69F30A Name — PAFS6 PAFS� — PAFS3 — PAFS1 — — — — — P�R — — — — Bit 7 Unimplemented, read as “0” Bit 6 PAFS6: Port A 6 Function Selection 0: I/O 1: TP0_0 Bit 5 PAFS5: Port A 5 Function Selection 0: I/O 1: TP1_1 Bit 4...
Page 84 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PBFS Register – HT69F40A/HT69F50A Name PBFS7 PBFS6 PBFS� PBFS4 — — — — — — — — P�R — — — — PBFS7: Port B 7 Function Selection Bit 7 0: I/O 1: TP1B_2 PBFS6: Port B 6 Function Selection Bit 6 0: I/O 1: TP1B_1 PBFS5: Port B 5 Function Selection Bit 5 0: I/O...
Page 85 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PDFS Register – HT69F30A Name PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0 P�R PDFS7: Port D 7 Function Selection Bit 7 0: I/O 1: SEG7 PDFS6: Port D 6 Function Selection Bit 6 0: I/O 1: SEG6 PDFS5: Port D 5 Function Selection Bit 5 0: I/O 1: SEG5 PDFS4: Port D 4 Function Selection Bit 4 0: I/O 1: SEG4 PDFS3: Port D 3 Function Selection Bit 3 0: I/O...
Page 86 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PDFS Register – HT69F40A/HT69F50A Name PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0 P�R PDFS7: Port D 7 Function Selection Bit 7 0: I/O 1: SEG7 or TP1B_2 PDFS6: Port D 6 Function Selection Bit 6 0: I/O 1: SEG6 or TP1B_1 PDFS5: Port D 5 Function Selection Bit 5 0: I/O 1: SEG5 or TP1B_0 PDFS4: Port D 4 Function Selection Bit 4 0: I/O 1: SEG4 or TP1A PDFS3: Port D 3 Function Selection Bit 3 0: I/O...
Page 87 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PEFS Register – HT69F30A/HT69F40A/HT69F50A Name PEFS7 PEFS6 PEFS� PEFS4 PEFS3 PEFS2 PEFS1 PEFS0 P�R PEFS7: Port E 7 Function Selection Bit 7 0: I/O 1: SEG15 PEFS6: Port E 6 Function Selection Bit 6 0: I/O 1: SEG14 PEFS5: Port E 5 Function Selection Bit 5 0: I/O 1: SEG13 PEFS4: Port E 4 Function Selection Bit 4 0: I/O 1: SEG12 PEFS3: Port E 3 Function Selection Bit 3 0: I/O...
Page 88 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PFFS Register – HT69F30A/HT69F40A/HT69F50A Name PFFS7 PFFS6 PFFS� PFFS4 PFFS3 PFFS2 PFFS1 PFFS0 P�R PFFS7: Port F 7 Function Selection Bit 7 0: I/O 1: SEG23 PFFS6: Port F 6 Function Selection Bit 6 0: I/O 1: SEG22 PFFS5: Port F 5 Function Selection Bit 5 0: I/O 1: SEG21 PFFS4: Port F 4 Function Selection Bit 4 0: I/O 1: SEG20 PFFS3: Port F 3 Function Selection Bit 3 0: I/O...
Page 89 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PGFS Register – HT69F40A/HT69F50A Name PGFS7 PGFS6 PGFS� PGFS4 PGFS3 PGFS2 PGFS1 PGFS0 P�R PGFS7: Port G 7 Function Selection Bit 7 0: I/O 1: SEG31 PGFS6: Port G 6 Function Selection Bit 6 0: I/O 1: SEG30 PGFS5: Port G 5 Function Selection Bit 5 0: I/O 1: SEG29 PGFS4: Port G 4 Function Selection Bit 4 0: I/O 1: SEG28 PGFS3: Port G 3 Function Selection Bit 3 0: I/O...
Page 90 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PHFS Register – HT69F50A Name PHFS7 PHFS6 PHFS� PHFS4 PHFS3 PHFS2 PHFS1 PHFS0 P�R PHFS7: Port H 7 Function Selection Bit 7 0: I/O 1: SEG39 PHFS6: Port H 6 Function Selection Bit 6 0: I/O 1: SEG38 PHFS5: Port H 5 Function Selection Bit 5 0: I/O 1: SEG37 PHFS4: Port H 4 Function Selection Bit 4 0: I/O 1: SEG36 PHFS3: Port H 3 Function Selection Bit 3 0: I/O...
Page 91 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM SFS Register – HT69F40A/HT69F50A Name SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0 P�R SFS7: TCK2 Source Selection Bit 7 0: PA2 1: PD2 SFS6: TCK1 Source Selection Bit 6 0: PA0 1: PD3 SFS5: TCK0 Source Selection Bit 5 0: PA2 1: PD1 SFS4: INT1 Source Selection Bit 4 0: PA0 1: PD0 SFS3: PD7 Special Function Selection Bit 3 0: SEG7...
Page 92: I/� Pin St�U�Tu�Es
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
Page 93: Timer Modules - Tm
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two or three individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Enhanced TM sections. Introduction The devices contain from two to three TMs depending upon which device is selected with each TM having a reference name of TM0, TM1, and TM2. Each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Enhanced Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Enhanced TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table.
Page 94: Tm Clo�K Sou
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TMn control registers. The clock source can be a ratio of either the system clock f or the internal high clock f , the f clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where...
Page 95 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. TM Input/Output Pin Control Register List • HT69F30A Register Name PAFS — PAFS6 PAFS� — PAFS3 — PAFS1 — — SFS6 SFS�...
Page 96 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PAFS Register – HT69F40A/HT69F50A Name — PAFS6 PAFS� — PAFS3 — PAFS1 — — — — — P�R — — — — Bit 7 Unimplemented, read as “0” Bit 6 PAFS6: Port A 6 Function Selection 0: I/O 1: TP0_0 Bit 5 PAFS5: Port A 5 Function Selection 0: I/O 1: TP2_1 Bit 4...
Page 97 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PDFS Register – HT69F40A/HT69F50A Name PDFS7 PDFS6 PDFS� PDFS4 PDFS3 PDFS2 PDFS1 PDFS0 P�R PDFS7: Port D 7 Function Selection Bit 7 0: I/O 1: SEG7 or TP1B_2 PDFS6: Port D 6 Function Selection Bit 6 0: I/O 1: SEG6 or TP1B_1 PDFS5: Port D 5 Function Selection Bit 5 0: I/O 1: SEG5 or TP1B_0 PDFS4: Port D 4 Function Selection Bit 4 0: I/O 1: SEG4 or TP1A PDFS3~PDFS0: Port D 3~0 Function Selection Bit 3~0 Described elsewhere.
Page 98 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM SFS Register – HT69F40A/HT69F50A Name SFS7 SFS6 SFS� SFS4 SFS3 SFS2 SFS1 SFS0 P�R SFS7: TCK2 Source Selection Bit 7 0: PA2 1: PD2 SFS6: TCK1 Source Selection Bit 6 0: PA0 1: PD3 SFS5: TCK0 Source Selection Bit 5 0: PA2 1: PD1 SFS4: INT1 Source Selection Bit 4 Described elsewhere. Bit 3 SFS3: PD7 Special Function Selection 0: SEG7 1: TP1B_2...
Page 99 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PA6/TP0_0 PAFS6 �utput PA1/TP0_1 (CTM) PAFS3 TCK0 Input PA2 o� PD1/TCK0 CTM Function Pin Control Block Diagram – HT69F30A/HT69F40A/HT69F50A PA3/TPn_0 PAFS3 PA� �utput PA�/TPn_1 PAFS� PA� Captu�e Input “0” (STM) PAFS�...
Page 100 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM PB4� PD4 CCRA �utput PB4 o� PD4/TP1A PBFS4� PDFS4 CCRA Captu�e Input “0” PBFS4� PDFS4 PB�� PD� PB� o� PD�/TP1B_0 PBFS�� PDFS� PB�� PD� PB6� PD6 PB6 o� PD6/TP1B_1 PBFS6� PDFS6 PB6�...
Page 101: P�Og�Amming Conside�Ations
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. TM Counte� Registe� (Read only) TMxDL TMxDH �-�it Buffe� TMxAL TMxAH TM CCRA Registe� (Read/W�ite) TMxBL TMxBH TM CCRB Registe�...
Page 102: Compact Type Tm - Ctm
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. Device TM Type TM Name. TM Input Pin TM Output Pin HT69F30A HT69F40A 10-�it CTM...
Page 103: Compa�T Type Tm Registe� Des
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 Tn�N...
Page 104 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TMnC0 Register Name TnPAU TnCK2 TnCK1 TnCK0 Tn�N TnRP2 TnRP1 TnRP0 P�R TnPAU: TMn Counter Pause Control Bit 7 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: f 001: f 010: f 011: f 100: f 101: Reserved 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source...
Page 105 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Bit 2~0 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
Page 106 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off.
Page 107: Compa�T Type Tm �Pe�Ating Modes
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match...
Page 108 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� ove�flow Counte� Value TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 CCRP=0 Counte� �lea�ed �y CCRP value 0x3FF CCRP > 0 Counte� Resume Resta�t CCRP Pause Stop CCRA Time Tn�N...
Page 109 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flow 0x3FF CCRA=0 Resume CCRA Pause Stop Counte� Resta�t CCRP Time Tn�N...
Page 110: Time�/Counte� Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
Page 111 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnDPX = 0; TnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when Tn�N �etu�ns high CCRP Counte� Stop if Pause Resume Tn�N �it low CCRA Time Tn�N TnPAU TnP�L...
Page 112 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnDPX = 1; TnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when Tn�N �etu�ns high CCRA Counte� Stop if Pause Resume Tn�N �it low CCRP Time Tn�N TnPAU TnP�L...
Page 113: Standard Type Tm - Stm
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. Device TM Type TM Name. TM Input Pin TM Output Pin HT69F30A 10-�it STM TCK1...
Page 114: Standa�D Type Tm Registe� Des
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1�N T1RP2...
Page 115 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM 10-bit STM Register Definitions – n=1 for HT69F30A and n=2 for HT69F40A • TMnC0 Register Name TnPAU TnCK2 TnCK1 TnCK0 Tn�N TnRP2 TnRP1 TnRP0 P�R TnPAU: TMn Counter Pause Control Bit 7 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes...
Page 116 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • TMnC1 Register - 10-bit STM Name TnM1 TnM0 TnI�1 TnI�0 Tn�C TnP�L TnDPX TnCCLR P�R TnM1~TnM0: Select TMn Operating Mode Bit 7~6 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode...
Page 117 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TnOC: TPn_0, TPn_1 Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no...
Page 118 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • TMnDL Register – 10-bit STM Name D� P�R TMnDL: TMn Counter Low Byte Register bit 7~bit 0 Bit 7~0 TMn 10-bit Counter bit 7~bit 0 • TMnDH Register – 10-bit STM Name — — — — — — D� — — — — —...
Page 119 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM 16-bit STM Register Definitions – HT69F50A • TM2C0 Register Name T2PAU T2CK2 T2CK1 T2CK0 T2�N — — — — — — P�R — — — T2PAU: TM2 Counter Pause Control Bit 7 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes...
Page 120 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • TM2C1 Register – 16-bit STM Name T2M1 T2M0 T2I�1 T2I�0 T2�C T2P�L T2DPX T2CCLR P�R Bit 7~6 T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T2IO1~T2IO0: Select TP2_0, TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode...
Page 121 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM T2OC: TP2_0, TP2_1 Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T2POL: TP2_0, TP2_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no...
Page 122 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM • TM2DL Register – 16-bit STM Name D� P�R TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 Bit 7~0 TM2 16-bit Counter bit 7~bit 0 • TM2DH Register – 16-bit STM Name D1� D� P�R Bit 7~0 TM2DH: TM2 Counter High Byte Register bit 7~bit 0 TM2 16-bit Counter bit 15~bit 8 • TM2AL Register – 16-bit STM Name D�...
Page 123: Standa�D Type Tm �Pe�Ating Modes
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0...
Page 124 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TnCCLR = 0; TnM[1:0] = 00 Counte� Counte� Value ove�flow CCRP = 0 CCRP > 0 Counte� �lea�ed �y CCRP value 0x3FF/ CCRP > 0 0xFFFF CCRP Pause Resume Counte� Stop Reset CCRA...
Page 125 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TnCCLR = 1; TnM[1:0] = 00 Counte� Value CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flows 0x3FF/ 0xFFFF CCRA = 0 CCRA Pause Resume Counte� Stop Reset CCRP...
Page 126: Time�/Counte� Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
Page 127 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM 10-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Pe�iod 12� 2�6 3�4 �12 76� �96 1024 Duty CCRA If f =16MHz, TM clock source select f /4, CCRP=100b and CCRA=128, The STM PWM output frequency=(f /4)/512=f /2048=7.8125kHz, duty=128/512=25% If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the...
Page 128 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnDPX = 0; TnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when Tn�N �etu�ns high CCRP Counte� Stop if Pause Resume Tn�N �it low CCRA Time Tn�N TnPAU TnP�L...
Page 129 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnDPX = 1; TnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when Tn�N �etu�ns high CCRA Counte� Stop if Pause Resume Tn�N �it low CCRP Time Tn�N TnPAU TnP�L...
Page 130: Single Pulse Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. L e a d i n g E d g e T r a i l i n g E d g e S / W C o m m a n d...
Page 131 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnM [1:0] = 10 ; TnI� [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when Tn�N �etu�ns high CCRA Counte� Stops Resume Pause �y softwa�e CCRP Time Tn�N Auto.
Page 132: Captu�E Input Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Rev. 1.20 ��to�e�...
Page 133 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Counte� Stop Reset CCRP Resume Pause Time Tn�N TnPAU A�tive A�tive A�tive edge edge edge TM �aptu�e pin TPn_x CCRA Int.
Page 134: Enhanced Type Tm - Etm
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Enhanced Type TM – ETM The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. Device TM Type TM Name. TM Input Pin TM Output Pin HT69F30A —...
Page 135 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1�N T1RP2 T1RP1 T1RP0 TM1C1 T1AM1 T1AM0 T1AI�1 T1AI�0 T1A�C...
Page 136 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM T1ON: TM1 Counter On/Off Control Bit 3 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the...
Page 137 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TM1C1 Register – 10-bit ETM Name T1AM1 T1AM0 T1AI�1 T1AI�0 T1A�C T1AP�L T1CDN T1CCLR P�R T1AM1~T1AM0: Select TM1 CCRA Operating Mode Bit 7~6 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Page 138 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM T1AOC: TP1A Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the...
Page 139 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TM1C2 Register – 10-bit ETM Name T1BM1 T1BM0 T1BI�1 T1BI�0 T1B�C T1BP�L T1PWM1 T1PWM0 P�R T1BM1~T1BM0: Select TM1 CCRB Operating Mode Bit 7~6 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Page 140 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero.
Page 141 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TM1AL Register – 10-bit ETM Name D� P�R TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 Bit 7~0 TM1 10-bit CCRA bit 7~bit 0 TM1AH Register – 10-bit ETM Name — — — — — — D� — — — — — — P�R —...
Page 142: Enhan�Ed Type Tm �Pe�Ating Modes
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register. CCRA CCRA CCRA CCRA CCRA Compare Single Timer/ Input ETM Operating Mode Match Output Pulse Counter Output Capture Mode Output Mode Mode Mode Mode...
Page 143 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� ove�flow Counte� Value TnCCLR = 0; TnAM [1:0] = 00 CCRP > 0 CCRP=0 Counte� �lea�ed �y CCRP value 0x3FF CCRP > 0 Counte� Resume Resta�t CCRP Pause Stop CCRA Time Tn�N...
Page 144 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� ove�flow Counte� Value TnCCLR = 0; TnBM [1:0] = 00 CCRP > 0 CCRP=0 Counte� �lea�ed �y CCRP value 0x3FF CCRP > 0 Counte� Resume Resta�t CCRP Pause Stop CCRB Time Tn�N...
Page 145 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 1; TnAM [1:0] = 00 CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flow 0x3FF CCRA=0 Resume CCRA Pause Stop Counte� Resta�t CCRP Time Tn�N...
Page 146 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 1; TnBM [1:0] = 00 CCRA = 0 CCRA > 0 Counte� �lea�ed �y CCRA value Counte� ove�flow 0x3FF CCRA=0 Resume CCRA Pause Stop Counte� Resta�t CCRB Time Tn�N...
Page 147: Time�/Counte� Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Timer/Counter Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared functions. PWM Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc.
Page 148 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Pe�iod 12� 2�6 3�4 �12 76� �96 1024 A Duty CCRA B Duty CCRB If f =12MHz, TM clock source select f /4, CCRP=100b, CCRA=128 and CCRB=256, The TPnA PWM output frequency=(f...
Page 149 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 0; Counte� Clea�ed �y CCRP TnAM [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 00 CCRP CCRA Counte� Resume Stop Pause Resta�t CCRB Time Tn�N TnPAU TnAP�L...
Page 150 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 1; TnBM [1:0] = 10; Counte� Clea�ed �y CCRA TnPWM [1:0] = 00 CCRA Counte� Resume Stop Pause Resta�t CCRB Time Tn�N TnPAU TnBP�L CCRP Int. Flag TnPF CCRB Int.
Page 151 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 0; TnAM [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 11 CCRP Counte� Stop Resta�t Resume CCRA Pause CCRB Time Tn�N TnPAU TnAP�L CCRA Int. Flag TnAF CCRB Int.
Page 152 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 11 CCRA Counte� Stop Resta�t Resume Pause CCRB Time Tn�N TnPAU TnBP�L CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int.
Page 153: Single Pulse �Utput Mode
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Single Pulse Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB_x output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB_x will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB_x. In this way the CCRA value can be used to control the pulse width of TPnA. The (CCRA-CCRB) value can be used to control the pulse width of TPnB_x. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used.
Page 154 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnAM [1:0] = 10� TnBM [1:0] = 10; Counte� stopped TnAI� [1:0] = 11� TnBI� [1:0] = 11 �y CCRA Counte� Reset CCRA when Tn�N �etu�ns high Counte� Stops Resume Pause �y softwa�e...
Page 155 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1,...
Page 156 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Counte� Value TnAM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Counte� Stop Reset CCRP Resume Pause Time Tn�N TnPAU A�tive A�tive A�tive edge edge edge TM �aptu�e pin TPnA CCRA Int.
Page 157 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TnBM1� TnBM0 = 01 Counte� Counte� Value ove�flow CCRP Counte� Stop Reset Pause Resume Time Tn�N �it TnPAU �it A�tive A�tive A�tive edges edge edge TM Captu�e Pin CCRB Int. Flag TnBF CCRP Int.
Page 158: Interrupts
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Time Base and LVD. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three...
Page 159 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Interrupt Register Contents • HT69F30A Name INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — TB0F INT1F INT0F TB0E INT1E INT0E INTC1 MF2F MF1F MF0F TB1F MF2E MF1E MF0E TB1E MFI0...
Page 160 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM INTC0 Register Name — TB0F INT1F INT0F TB0E INT1E INT0E — P�R — Bit 7 Unimplemented, read as “0” Bit 6 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request INT0F: INT0 interrupt request flag Bit 4 0: No request 1: Interrupt request TB0E: Time Base 0 interrupt control Bit 3 0: Disable 1: Enable INT1E: INT1 interrupt control Bit 2...
Page 161 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM INTC1 Register Name MF2F MF1F MF0F TB1F MF2E MF1E MF0E TB1E P�R MF2F: Multi-function interrupt 2 request flag Bit 7 0: No request 1: Interrupt request MF1F: Multi-function interrupt 1 request flag Bit 6 0: No request 1: Interrupt request MF0F: Multi-function interrupt 0 request flag Bit 5 0: No request 1: Interrupt request TB1F: Time Base 1 interrupt request flag Bit 4 0: No request 1: Interrupt request MF2E: Multi-function interrupt 2 control Bit 3 0: Disable 1: Enable MF1E: Multi-function interrupt 1 control...
Page 162 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM MFI0 Register – HT69F40A/HT69F50A Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE P�R T2AF: TM2 Comparator A match interrupt request flag Bit 7 0: No request 1: Interrupt request T2PF: TM2 Comparator P match interrupt request flag Bit 6 0: No request 1: Interrupt request T0AF: TM0 Comparator A match interrupt request flag Bit 5 0: No request 1: Interrupt request T0PF: TM0 Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request T2AE: TM2 Comparator A match interrupt control Bit 3 0: Disable...
Page 163 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM MFI1 Register – HT69F40A/HT69F50A Name — T1BF T1AF T1PF — T1BE T1AE T1PE — — P�R — — Bit 7 Unimplemented, read as “0” Bit 6 T1BF: TM1 Comparator B match interrupt request flag 0: No request 1: Interrupt request Bit 5 T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request T1PF: TM1 Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3...
Page 164: Inte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or Comparator B match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI" , which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
Page 165: Inte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM EMI auto disa�led in ISR Legend Request Flag� no auto �eset in ISR Inte��upt Request Ena�le Maste� Vector P�io�ity Request Flag� auto �eset in ISR Name Flags Bits Ena�le High INT0 Pin INT0F INT0E...
Page 166: Exte�Nal Inte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Multi-function Interrupt Within this device there are up to three Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, EEPROM Interrupt and LVD interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF, are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine...
Page 167: Time Base Inte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, f , originates from the internal clock source f or f /4. And then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using a bit in the TBC register.
Page 168: Tm Inte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM EEPROM Interrupt The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM write operation ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the EEPROM Interrupt enable bit, DEE, and Muti- function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM write operation ends, a subroutine call to the respective Multi-function Interrupt vector, will take place.When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically...
Page 169: Inte
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.
Page 170: Low Voltage Detector - Lvd
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Name — — LVD� LVDEN —...
Page 171: Lvd �Pe�Ation
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry to stabilise before reading the LVDS LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions. V D D L V D L V D E N L V D O L V D S LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-...
Page 172: Lcd Driver
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LCD Driver For large volume applications, which incorporate an LCD in their design, the use of a custom display rather than a more expensive character based display reduces costs significantly. However, the corresponding COM and SEG signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper LCD operation to occur. These devices all contain an LCD Driver function, which with their internal LCD signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom LCDs. All devices include a wide range of options to enable LCD displays of various types to be driven. The table shows the range of options available across the device range. Device Duty Bias Bias Type...
Page 173 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM �0H �0H SEG0 SEG0 �1H SEG1 �1H SEG1 SEG21 9�H SEG21 9�H SEG22 SEG22 SEG23 SEG23 SEG24 9�H : Unused� �ead as “0” 24 SEG x 4 COM 25 SEG x 3 COM HT69F30A LCD Memory Map �0H SEG0...
Page 174: Lcd Registe
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LCD Register There is one control register, named as LCDC, in the Data Memory used to control the various setup features of the LCD Driver. Various bits in this registers control functions such as LCD wave type, duty type, bias type, bias resistor selection as well as overall LCD enable and disable. The LCDEN bit in the LCDC register, which provides the overall LCD enable/disable function, will only be effective when the device is in the NOAMRL, SLOW or IDLE Mode. If the device is in the SLEEP Mode then the display will always be disabled. Bits, RSEL0 and RSEL1, in the LCDC register select the internal bias resistors to supply the LCD panel with the correct bias voltages. A choice to best match the LCD panel used in the application can be selected also to minimise bias current. The TYPE bit in the same register is used to select whether Type A or Type B LCD control signals are used. LCDC Register Name TYPE — DTYC — BIAS RSEL1 RSEL0 LCDEN — — P�R — — Bit 7 TYPE: LCD Wave Type Control 0: Type A 1: Type B Bit 6...
Page 175: Lcd Reset Fun�Tion
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LCD Reset Function The LCD has an internal reset function that is an OR function of the inverted LCDEN bit in the LCDC register and the Sleep function. When the LCDEN bit is set to 1 to enable the LCD driver function before the device enters the SLEEP mode, the LCD function will be reset after the device enters the SLEEP mode. Clearing the LCDEN bit to zero will also reset the LCD function. LCDEN SLEEP Mode Reset LCD �ff √ �n √ �ff �n √ LCD Reset Function Clock Source The LCD clock source is the internal clock signal, f , divided by 8, using an internal divider circuit. The f internal clock is supplied by either the LIRC or LXT oscillator, the choice of which is determined by a configuration option. For proper LCD operation, this arrangement is provided to generate an ideal LCD clock source frequency of 4kHz. Clock Source LCD Clock Frequency LIRC...
Page 176: Lcd Voltage Sou
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LCD Voltage Source Biasing The time and amplitude varying signals generated by the LCD Driver function require the generation of several voltage levels for their operation. The number of voltage levels used by the signal depends upon the value of the BIAS bit in the LCDC register. The device can have either R type or C type biasing selected via a configuration option. Selecting the C type biasing will enable an internal charge pump whose multiplier ratio can be selected using an additional configuration option. For R type biasing an external LCD voltage source must be supplied on pin VLCD to generate the internal biasing voltages. This could be the microcontroller power supply or some other voltage source. For the R type 1/2 bias selection, three voltage levels V and V are utilised. The voltage V is equal to the externally supplied voltage source applied to pin VLCD. The voltage V is generated internally by the microcontroller and will have a value equal to V /2. For the R type 1/3 bias selection, four voltage levels V and V are utilised. The voltage V...
Page 177: Lcd Wavefo�M Timing Diag�Am
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM LCD Waveform Timing Diagram The accompanying timing diagrams depict the display driver signals generated by the microcontroller for various values of duty and bias. The huge range of various permutations only permits a few types to be displayed here. D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f R t y p e b i a s L C D C t y p e b i a s...
Page 178 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f R t y p e b i a s L C D C t y p e b i a s...
Page 179 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f R t y p e b i a s L C D C t y p e b i a s...
Page 180 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM During Reset or LCD Off COM0, COM1, COM2 All segment outputs 1 Frame Normal Operation Mode COM0 COM1 COM2 All segments are OFF COM0 side segments are ON COM1 side segments are ON COM2 side segments are ON COM0, 1 side segments are ON COM0, 2 side segments are ON...
Page 181 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM D u r i n g R e s e t o r L C D F u n c t i o n i s s w i t c h e d o f f During Reset or LCD Off R t y p e b i a s L C D...
Page 182 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Programming Considerations Certain precautions must be taken when programming the LCD. One of these is to ensure that the LCD Memory is properly initialised after the microcontroller is powered on. Like the General Purpose Data Memory, the contents of the LCD Memory are in an unknown condition after power-on. As the contents of the LCD Memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. Consideration must also be given to the capacitive load of the actual LCD used in the application. As the load presented to the microcontroller by LCD pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the COM lines which may be connected to many LCD pixels. The accompanying diagram depicts the equivalent circuit of the LCD. One additional consideration that must be taken into account is what happens when the microcontroller enters the Idle or Slow Mode. The LCDEN control bit in the LCDC register permits the display to be powered off to reduce power consumption. If this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption...
Page 183: Configuration Options
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. Options High Speed System �s�illato� Sele�tion – f HXT� ERC� EC o� HIRC HXT Mode Sele�tion 1MHz~12MHz o� 4��kHz Low Speed System �s�illato� Sele�tion – f LXT o�...
Page 184: Application Circuits
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Application Circuits COM[3:0] SEG[47:0] VLCD Panel VMAX 100KΩ PA7/RES 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF PB0/OSC1 Circuit PB1/OSC2 PA0/INT1/TCK1 PA1/TP0_1 PB2/XT1 PA2/TCK0/TCK2 Circuit PA3/TP2_0 PB3/XT2 PA4/INT0 PA5/TP2_1 PA6/TP0_0 PB4/TP1A PB5/TP1B_0 PB6/TP1B_1 PB7/TP1B_2 PC3~PC6 PD0~PD7...
Page 185: Instruction Set
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5µs and branch or call instructions would be implemented within 1µs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ″CLR PCL″ or ″MOV PCL, A″. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to...
Page 186 I/O Flash 8-Bit MCU with LCD & EEPROM Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...
Page 187: Instruction Set Summary
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A�[m] Add Data Memo�y to ACC Z� C� AC� �V ADDM A�[m] Add ACC to Data Memo�y Note Z�...
Page 188 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Mnemonic Description Cycles Flag Affected Data Move M�V A�[m] Move Data Memo�y to ACC None M�V [m]�A Move ACC to Data Memo�y Note None M�V A�x Move immediate data to ACC None Bit Operation CLR [m].i...
Page 189: Instruction Definition
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x...
Page 190 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer...
Page 191 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1.
Page 192 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
Page 193 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s) None...
Page 194 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None Rotate Data Memory right through Carry RRC [m] Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C...
Page 195 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None Skip if increment Data Memory is 0...
Page 196 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC...
Page 197 HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None...
Page 198: Package Information
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.20 19� ��to�e� 0�� 201�...
Page 199: 4�-Pin Lqfp (7Mm×7Mm) �Utline Dimensions
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM 48-pin LQFP (7mm×7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.3�4 BSC — — 0.276 BSC — — 0.3�4 BSC — — 0.276 BSC — — 0.020 BSC —...
Page 200: 64-Pin Lqfp (7Mm×7Mm) �Utline Dimensions
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM 64-pin LQFP (7mm × 7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.3�4 BSC — — 0.276 BSC — — 0.3�4 BSC — — 0.276 BSC — —...
Page 201: 0-Pin Lqfp (10Mm×10Mm) �Utline Dimensions
HT69F30A/HT69F40A/HT69F50A TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM 80-pin LQFP (10mm × 10mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ― 0.472 BSC ― ― 0.394 BSC ― ― 0.472 BSC ― ― 0.394 BSC ― ―...
Page 202 Howeve�� Holtek assumes no �esponsi�ility a�ising f�om the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek makes no wa��anty o� �ep�esentation that su�h appli�ations will �e suita�le without fu�the� modifi�ation� no� �e�ommends the use of its p�odu�ts fo�...

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Holtek TinyPower HT69F40A Manual

Features

General Description

Selection Table

Block Diagram

Pin Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

LVD & LVR Electrical Characteristics

LCD D.C. Characteristics

Power-On Reset Characteristics

System Architecture

Flash Program Memory

Data Memory

Special Function Register Description

EEPROM Data Memory

Oscillator

Operating Modes and System Clocks

Watchdog Timer

Reset and Initialisation

Input/Output Ports

Timer Modules - TM

Compact Type TM - CTM

Standard Type TM - STM

Enhanced Type TM - ETM

Interrupts

Low Voltage Detector - LVD

LCD Driver

Configuration Options

Application Circuits

Instruction Set

Instruction Set Summary

Instruction Definition

Package Information

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