Holtek HT67F2350 Manual page 206

UnSR Register
The UnSR register is the status register for the UARTn, which can be read by the program to
determine the present status of the UARTn. All flags within the UnSR register are read only and
further explanations are given below.
Bit 7
Name PERRn
R/W R
POR 0
Bit 7 PERRn: Parity error flag
0: No parity error is detected
1: Parity error is detected
The PERRn flag is the parity error flag. When this read only flag is "0", it indicates a
parity error has not been detected. When the flag is "1", it indicates that the parity of
the received word is incorrect. This error flag is applicable only if Parity mode (odd or
even) is selected. The flag can also be cleared by a software sequence which involves
a read to the status register UnSR followed by an access to the TXR_RXRn data
register.
NFn: Noise flag
Bit 6
0: No noise is detected
1: Noise is detected
The NFn flag is the noise flag. When this read only flag is "0", it indicates no noise
condition. When the flag is "1", it indicates that the UARTn has detected noise on the
receiver input. The NFn flag is set during the same cycle as the RXIFn flag but will not
be set in the case of as overrun. The NFn flag can be cleared by a software sequence
which will involve a read to the status register UnSR followed by an access to the
TXR_RXRn data register.
Bit 5 FERRn: Framing error flag
0: No framing error is detected
1: Framing error is detected
The FERRn flag is the framing error flag. When this read only flag is "0", it indicates
that there is no framing error. When the flag is "1", it indicates that a framing error
has been detected for the current character. The flag can also be cleared by a software
sequence which will involve a read to the status register UnSR followed by an access
to the TXR_RXRn data register.
Bit 4 OERRn: Overrun error flag
0: No overrun error is detected
1: Overrun error is detected
The OERRn flag is the overrun error flag which indicates when the receiver buffer has
overflowed. When this read only flag is "0", it indicates that there is no overrun error.
When the flag is "1", it indicates that an overrun error occurs which will inhibit further
transfers to the TXR_RXRn receive data register. The flag is cleared by a software
sequence, which is a read to the status register UnSR followed by an access to the
TXR_RXRn data register.
RIDLEn: Receiver status
Bit 3
0: data reception is in progress (data being received)
1: no data reception is in progress (receiver is idle)
The RIDLEn flag is the receiver status flag. When this read only flag is "0", it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLEn bit is
"1" indicating that the UARTn receiver is idle and the RXn pin stays in logic high
condition.
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
6 5 4
NFn FERRn OERRn
R R R
0 0 0
206
HT67F2350/HT67F2360
HT67F2370/HT67F2390
3 2 1
RIDLEn RXIFn TIDLEn
R R R
1 0 1
May 16, 2019
0
TXIFn
R
1