Holtek HT67F2350 Manual page 213

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
Transmitting Data
When the UARTn is transmitting data, the data is shifted on the TXn pin from the shift register,
with the least significant bit LSB first. In the transmit mode, the TXR_RXRn register forms a buffer
between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format
has been selected, then the MSB will be taken from the TX8n bit in the UnCR1 register. The steps to
initiate a data transfer can be summarized as follows:
• Make the correct selection of the BNOn, PRTn, PRENn and STOPSn bits to define the required
word length, parity type and number of stop bits.
• Setup the BRGn register to select the desired baud rate.
• Set the TXENn bit to ensure that the UARTn transmitter is enabled and the TXn pin is used as a
UARTn transmitter pin.
• Access the UnSR register and write the data that is to be transmitted into the TXR_RXRn
register. Note that this step will clear the TXIFn bit.
This sequence of events can now be repeated to send additional data. It should be noted that when
TXIFn=0, data will be inhibited from being written to the TXR_RXRn register. Clearing the TXIFn
flag is always achieved using the following software sequence:
1. A UnSR register access
2. A TXR_RXRn register write execution
The read-only TXIFn flag is set by the UARTn hardware and if set indicates that the TXR_RXRn
register is empty and that other data can now be written into the TXR_RXRn register without
overwriting the previous data. If the TEIEn bit is set, then the TXIFn flag will generate an interrupt.
During a data transmission, a write instruction to the TXR_RXRn register will place the data into the
TXR_RXRn register, which will be copied to the shift register at the end of the present transmission.
When there is no data transmission in progress, a write instruction to the TXR_RXRn register will
place the data directly into the shift register, resulting in the commencement of data transmission,
and the TXIFn bit being immediately set. When a frame transmission is complete, which happens
after stop bits are sent or after the break frame, the TIDLEn bit will be set. To clear the TIDLEn bit
the following software sequence is used:
1. A UnSR register access
2. A TXR_RXRn register write execution
Note that both the TXIFn and TIDLEn bits are cleared by the same software sequence.
Transmitting Break
If the TXBRKn bit is set, then the break characters will be sent on the next transmission. Break
character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a break
character is to be transmitted, then the TXBRKn bit must be first set by the application program and
then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRKn bit is continually
kept at a logic high level, then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRKn bit, the transmitter will finish transmitting
the last break character and subsequently send out one or two stop bits. The automatic logic high at
the end of the last break character will ensure that the start bit of the next frame is recognized.
Rev. 1.60 213 May 16, 2019