Spia Bus Enable/Disable; Spia Operation - Holtek HT67F2350 Manual

SPIA Bus Enable/Disable

To enable the SPIA bus, set SACSEN=1 and SCSA=0, then wait for data to be written into the
SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD
(TXRX buffer) register, then transmission or reception will start automatically. When all the data has
been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received
on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in.
When the SPIA bus is disabled, the SCKA, SDIA, SDOA and SCSA pins can become I/O pins or
other pin-shared functions using the corresponding pin-shared function selection bits.

SPIA Operation

All communication is carried out using the 4-line interface for either Master or Slave Mode.
The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting
this bit high will enable the SPIA interface by allowing the
be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled
and the SCSA line will be an I/O pin or other pin-shared functions and can therefore not be used for
control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are
set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master
Mode the SCKA line will be either high or low depending upon the clock polarity selection bit
SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition.
If SPIAEN is low, then the bus will be disabled and SCSA, SDIA, SDOA and SCKA pins will all
become I/O pins or other pin-shared functions using the corresponding pin-shared function selection
bits. In the Master Mode the Master will always generate the clock signal. The clock and data
transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode,
the clock signal will be received from an external master device for both data transmission and
reception. The following sequences show the order to be followed for data transfer in both Master
and Slave Mode.
Master Mode:
• Step 1
Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control
register.
• Step 2
Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted
first, this must be same as the Slave device.
• Step 3
Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface.
• Step 4
For write operations: write the data to the SPIAD register, which will actually place the data into
the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5.
For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer
until all the data has been received at which point it will be latched into the SPIAD register.
• Step 5
Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal
to zero then go to the following step.
• Step 6
Check the SATRF bit or wait for a SPIA serial bus interrupt.
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
202
HT67F2350/HT67F2360
HT67F2370/HT67F2390
SCSA line to be active, which can then
May 16, 2019