Holtek HT67F2350 Manual page 198

SPIAC0 Register
Bit 7
Name SASPI2
R/W R/W
POR 1
Bit 7~5 SASPI2~SASPI0: SPIA Master/Slave clock select
000: SPIA master mode with clock f
001: SPIA master mode with clock f
010: SPIA master mode with clock f
011: SPIA master mode with clock f
100: SPIA master mode with clock PTM0 CCRP match frequency/2
101: SPIA slave mode
11x: SPIA disable
Bit 4~2 Unimplemented, read as "0"
Bit 1 SPIAEN: SPIA Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit
is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and
lines will lose the SPI function and the SPIA operating current will be reduced to a
minimum value. When the bit is high the SPIA interface is enabled.
SPIAICF: SPIA Incomplete Flag
Bit 0
0: SPIA incomplete condition not occurred
1: SPIA incomplete condition occurred
This bit is only available when the SPIA is configured to operate in an SPIA slave
mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits
both being set to 1 but the
before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1
together with the SATRF bit. When this condition occurs, the corresponding interrupt
will occur if the interrupt function is enabled. However, the SATRF bit will not be set
to 1 if the SPIAICF bit is set to 1 by software application program.
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
6 5 4
SASPI1 SASPI0 —
R/W R/W —
1 1 —
/4
SYS
/16
SYS
/64
SYS
SUB
line is pulled high by the external master device
SCSA
198
HT67F2350/HT67F2360
HT67F2370/HT67F2390
3 2 1
— — SPIAEN SPIAICF
— — R/W
— — 0
May 16, 2019
0
R/W
0
SCSA