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Holtek HT66F60A Manual

A/d flash mcu with eeprom
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A/D Flash MCU with EEPROM
HT66F60A
HT66F70A
Revision: V1.40
Date: ����st ��� �01�
����st ��� �01�

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Summary of Contents for Holtek HT66F60A

  • Page 1: External Interr

    A/D Flash MCU with EEPROM HT66F60A HT66F70A Revision: V1.40 Date: ����st ��� �01� ����st ��� �01�...

  • Page 2: Table Of Contents

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Table of Contents Features ......................7 CPU Feat�res ........................� Peripheral Feat�res ........................ � General Description ..................8 Selection Table ....................8 Block Diagram ....................9 Pin Assignment ....................10 Pin Description ....................12 Absolute Maximum Ratings ................
  • Page 3 HT66F60A/HT66F70A A/D Flash MCU with EEPROM EEPROM Data Memory .................. 46 EEPROM Data Memory Str�ct�re ..................46 EEPROM Re�isters ......................46 Readin� Data from the EEPROM ..................4� Writin� Data to the EEPROM ....................4� Write Protection ........................4� EEPROM Interr�pt ........................ 4�...

  • Page 4: Serial Interface Mod�Le Interr�Pts

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM I/O Pin Str�ct�res ........................93 Pro�rammin� Considerations ....................94 Timer Modules – TM ..................94 Introd�ction ........................... 94 TM Operation ........................95 TM Clock So�rce ........................95 TM Interr�pts ......................... 95 TM External Pins ........................96 TM Inp�t/O�tp�t Pin Control ....................

  • Page 5: Pro�Ram Co�Nter

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Comparators ....................159 Comparator Operation ......................159 Comparator Re�isters ......................160 Comparator Interr�pt ......................16� Pro�rammin� Considerations ....................16� Serial Interface Module – SIM ..............162 SPI Interface ........................16� SPI Re�isters ........................164 SPI Comm�nication ......................

  • Page 6: Rithmetic And Lo�Ic Unit

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Low Voltage Detector – LVD ............... 207 LVD Re�ister ........................�0� LVD Operation ........................�0� SCOM Function for LCD ................209 LCD Operation ........................�09 LCD Bias Control ........................ �09 Configuration Options ................. 210 Application Circuits ..................

  • Page 7: Features

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Features CPU Features • Operating Voltage: =8MHz: 2.2V~5.5V ♦ =12MHz: 2.7V~5.5V ♦ =16MHz: 4.5V~5.5V ♦ • Up to 0.25μs instruction cycle with 16MHz system clock at V • Power down and wake-up functions to reduce power consumption • Five oscillators: External Crystal -- HXT ♦ External 32.768kHz Crystal -- LXT ♦ External RC -- ERC ♦ Internal RC -- HIRC ♦ Internal 32kHz RC -- LIRC ♦ • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 8MHz ocilllator requires no external components • All instructions executed in 1~3 instruction cycles • Table read instructions •...

  • Page 8: General Description

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM General Description The HT66Fx0A series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontrollers, designed for a wide range of applications. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter and dual comparator functions.

  • Page 9: Block Diagram

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Block Diagram L o w W a t c h d o g V o l t a g e T i m e r D e t e c t R e s e t...

  • Page 10: Pin Assignment

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pin Assignment 4� 4� 46 45 44 43 4� 41 40 39 3� 3� PF1/�N11/C1P PB�/SDI/SD� PF0/�N10/C1N PD6/SCK/SCL � PE�/�N9/INT1 PD�/SCS PE6/�N�/INT0 PC�/PCK/TCK�/C0X PC3/PINT/TP�/TP�B/TP�I/C1X 3� PC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINT HT66F60A/HT66F70A PB4/XT� PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK � 48 LQFP-A PB3/XT1 PD0/TP3/TP3B/SCS/TCK�...

  • Page 11: Introd�Ction

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM 4� 4� 46 45 44 43 4� 41 40 39 3� 3� PF1/�N11/C1P PB�/SDI/SD� PF0/�N10/C1N PD6/SCK/SCL � PE�/�N9/INT1 PD�/SCS PE6/�N�/INT0 PC�/PCK/TCK�/C0X PC3/PINT/TP�/TP�B/TP�I/C1X 3� PC4/INT�/TCK3/TP�/TP�B/TP�I/INT0/PINT HT66V70A PB4/XT� 48 LQFP-A PC5/INT3/TP0/TP0B/TP1B/TP1BB/TP1IB/INT1/PCK � PB3/XT1 PD0/TP3/TP3B/SCS/TCK� � �9 VSS�...

  • Page 12: Pin Description

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pin Description Pad Name Function Description P�WU P�0 CMOS General p�rpose I/O. Re�ister enabled p�ll-�p and wake-�p P�PU P�0/ICPD�/ OCDSD� ICPD� — CMOS ICP Data/�ddress OCDSD� — CMOS OCDS Data/�ddress� for EV chip only P�WU...
  • Page 13 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pad Name Function Description PBPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PB0/RES — Reset pin PBPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PB1/OSC1 OSC1 — HXT/ERC oscillator pin & EC mode inp�t pin PB�...
  • Page 14 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pad Name Function Description PCPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PCS� INTEG INT� INTC3 — External Interr�pt � IFS0 TCK3 IFS1 — TM3 inp�t PC4/INT�/TCK3/ TP� PCS1 — CMOS TM� o�tp�t TP�/TP�B/TP�I/ INT0/PINT TP�B...
  • Page 15 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pad Name Function Description PDPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PDS0 TP� PDS0 — CMOS TM� o�tp�t TP�B PDS0 — CMOS TM� inverted o�tp�t PD1/TP�/TP�B/ TP�I IFS� — TM� inp�t TP�I/SDO/SCK/ PDS0 —...
  • Page 16 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pad Name Function Description PEPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PES0 PES0 SCK� CMOS SPI� serial clock PE1/SCK�/INT1 IFS5 INTEG INT1 INTC0 — External Interr�pt 1 IFS0 PEPU PE� CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PES1 SDI�...
  • Page 17 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pad Name Function Description PG� PGPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PG�/TCK4 TCK4 — — TM4 inp�t PGPU CMOS General p�rpose I/O. Re�ister enabled p�ll-�p PGS1 PG3/TP4/ PGS1 — CMOS TM4 o�tp�t...

  • Page 18: Absolute Maximum Ratings

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pad Name Function Description VSS� VSS� — — I/O Pad Power s�pply. Gro�nd Note: I/T: Input type; O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option ST: Schmitt Trigger input; CMOS: CMOS output; NMOS: NMOS output HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator Absolute Maximum Ratings Supply Voltage ....................V −0.3V to V +6.0V Input Voltage ....................V −0.3V to V +0.3V Storage Temperature ....................-50˚C to 125˚C Operating Temperature .
  • Page 19 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — m� No load� f =6MHz� �DC off� WDT enable — �.0 m� Operatin� C�rrent — 1.� �.0 m� No load� f =�MHz� �DC off�...
  • Page 20 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions No load� system H�LT� �DC off� ─ μA Standby C�rrent (IDLE0) WDT enable� f =3��6�Hz� STB� (LXT� f =off� f — �.� μA LXTLP=1 —...

  • Page 21: A.c. Characteristics

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM A.C. Characteristics Ta=�5°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Condition �.�~5.5V — � System clock (HXT) — �.�~5.5V — 1� SYS1 4.5~5.5V — System clock (ERC) 5V Ta=�5°C� External R =1�0kΩ -�% �...

  • Page 22: A/D Converter Electrical Characteristics

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM A/D Converter Electrical Characteristics Ta=25˚C Test Conditions Symbol Parameter Min. Typ. Max. Unit Condition A/D Converter Operating Voltage — — — A/D Converter Input Voltage — — — A/D Converter Reference Voltage — —...

  • Page 23: Comparator Electrical Characteristics

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions — For LVR enable, LVD off→on — — μs LVDO stable time LVDS — For LVR disable, LVD off→on — — μs Software Reset Width to Reset —...

  • Page 24: System Architecture

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator...
  • Page 25 HT66F60A/HT66F70A A/D Flash MCU with EEPROM F e t c h I n s t . 1 E x e c u t e I n s t . 1 M O V A , [ 1 2 H ] F e t c h I n s t .

  • Page 26: Stack

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P r o g r a m C o u n t e r T o p o f S t a c k...

  • Page 27: Flash Program Memory

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 16K×16 bits to 32K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries information. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers.

  • Page 28: Special Vectors

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 0000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD[m]” or “TABRDL[m]” instructions respectively when the memory [m] is located in current page. If the memory [m] is located in other pages, the data can be retrieved from the program memory using the “LTABRD[m]” or “LTABRDL[m]” instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. The accompanying diagram illustrates the addressing data flow of the look-up table. P r o g r a m...
  • Page 29 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is “3F00H” which refers to the start address of the last page within the 16K Program Memory of the HT66F60A device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “3F06H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m] instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

  • Page 30: In Circ�It Pro�Rammin� - Icp

    In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPD� P�0 Pro�rammin� Serial Data ICPCK P�� Pro�rammin� Clock Power S�pply...

  • Page 31: On-Chip Deb�� S�Pport Data/�Ddress Inp�T/O�Tp�T

    HT66V70A EV chip for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the HT66Fx0A series of devices will have no effect in the HT66V70A EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description OCDSD� OCDSD� On-Chip Deb�� S�pport Data/�ddress inp�t/o�tp�t...
  • Page 32 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • FC0 Register Name CFWEN FMOD� FMOD1 FMOD0 FWPEN FRDEN Bit 7 CFWEN: Flash Memory Write enable control 0: Flash memory write function is disabled 1: Flash memory write function has been successfully enabled When this bit is cleared to 0 by application program, the Flash memory write function is disabled. Note that writing a “1” into this bit results in no action. This bit is used to indicate that the Flash memory write function status. When this bit is set to 1 by hardware, it means that the Flash memory write function is enabled successfully. Otherwise, the Flash memory write function is disabled as the bit content is zero. FMOD2~FMOD0: Mode selection Bit 6~4 000: Write program memory 001: Page erase program memory...
  • Page 33 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • FC1 Register Name D� D� Bit 7~0 55H: whole chip reset When user writes 55H to this register, it will generate a reset signal to reset whole chip. • FC2 Register Name — — — — — — — CLWB — — — — — — — — — — — —...
  • Page 34 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • FD1L Register Name D� D� Bit 7~0 The second Flash Memory data [7:0] • FD1H Register Name D1� D� Bit 7~0 The second Flash Memory data [15:8] • FD2L Register Name D� D� Bit 7~0 The third Flash Memory data [7:0] • FD2H Register Name D1� D� Bit 7~0 The third Flash Memory data [15:8] • FD3L Register Name D�...

  • Page 35: 4�-Pin Lqfp (�Mm×�Mm) O�Tline Dimensions

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Flash Memory Write Function Enable Procedure In order to allow users to change the Flash memory data through the IAP control registers, users must first enable the Flash memory write operation by the following procedurce: • Write “110” into the FMOD2~FMOD0 bits to select the FWEN mode. • Set the FWPEN bit to “1”. The step 1 and step 2 can be executed simultaneously. • The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively. • A counter with a time-out period of 300μs will be activated to allow users writing the correct pattern data into the FD1L/FD1H~FD3L/FD3H register pairs. The counter clock is derived from LIRC oscillator. • If the counter overflows or the pattern data is incorrect, the Flash memory write operation will not be enabled and users must again repeat the above procedure. Then the FWPEN bit will automatically be cleared to 0 by hardware. • If the pattern data is correct before the counter overflows, the Flash memory write operation will be enabled and the FPWEN bit will automatically be cleared to 0 by hardware. The CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write operation is successfully enabled.

  • Page 36: 64-Pin Lqfp (�Mm×�Mm) O�Tline Dimensions

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Write Flash Memory Flash Memory Write F�nction Enable Proced�re Set Pa�e Erase address: F�RH/F�RL Set FMOD [�:0]=001 & FWT=1 → Select “Pa�e Erase mode” & Initiate write operation FWT=0 ? Set FMOD [�:0]=000 → Select “Write Flash Mode”...
  • Page 37 0000 0001 � 0000 0010 0000 0010 F�RL [5:0]: don’t care �5� 0011 1111 �53 0011 1111 �54 0011 1111 �55 0011 1111 50� 0111 1111 0111 1111 0111 1111 0111 1111 Note: There are 256 IAP erase pages in the HT66F60A device while there are 512 IAP erase pages in the HT66F70A device. Rev. 1.40 3� ����st ��� �01�...
  • Page 38 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Read Flash Memory Set FMOD [�:0]=011 & FRDEN=1 Set Flash �ddress re�isters F�H=xxh� F�L=xxh Set FRD=1 FRD=0 ? Read data val�e: FD0L=xxh� FD0H=xxh Read Finish ? Clear FWEN bit Read Flash Memory Procedure Note: When the FWT or FRD bit is set to 1, the MCU is stopped.

  • Page 39: Data Memory

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory is divided into several sections, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sections is categorized into two types, the Special Purpose Data...

  • Page 40: General P�Rpose Data Memory

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Section 0 Special P�rpose Data Memory 40H in section 1 �FH �0H �FH in section 1 General P�rpose Data Memory Section 0 Section 1 Section � Section N N=� for HT66F60�; N=15 for HT66F�0�...
  • Page 41 Un�sed SMOD� �FH SCOMC Un�sed : Un�sed� read as 00H : Un�sed� read as 00H HT66F60� Special P�rpose Data Memory HT66F�0� Special P�rpose Data Memory HT66F60A Special Purpose Data Memory HT66F70A Special Purpose Data Memory Rev. 1.40 ����st ��� �01�...

  • Page 42: Special Function Register Description

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Section 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory section. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation.

  • Page 43: Bank Pointer - Bp

    Device HT66F60� — — — — — — — HT66F�0� — — — — — — BP Register List BP Register – HT66F60A Name — — — — — — — — — — — — — — — —...

  • Page 44: Pro�Ram Co�Nter Low Re�Ister - Pcl

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller.
  • Page 45 HT66F60A/HT66F70A A/D Flash MCU with EEPROM STATUS Register Name �C “x”: �nknown Bit 7 SC: The result of the “XOR” operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The the operational result of different flags for different instuctions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag willl not be affected. Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag...

  • Page 46: Eeprom Data Memory

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM EEPROM Data Memory These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product...

  • Page 47: Readin� Data From The Eeprom

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM EEC Register Name — — — — WREN RDEN — — — — — — — — Bit 7~4 Unimplemented, read as “0” Bit 3 WREN: Data EEPROM write operation enable 0: Disable 1: Enable This is the Data EEPROM Write Operation Enable bit which must be set high before Datat EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: Data EEPROM write control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN bit has not first been set high.

  • Page 48: Writin� Data To The Eeprom

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer pairs, MP1L/MP1H and MP2L/MP2H, will be...

  • Page 49: Pro�Rammin� Examples

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Programming Examples Reading Data from the EEPROM – Polling Mothod MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, 040H ; setup memory pointer MP1L MOV MP1L, A ; MP1 points to EEC register MOV A, 01H ; setup memory pointer MP1H MOV MP1H, A SET IAR1.1 ; set RDEN bit, enable read operations SET IAR1.0 ; start Read Cycle - set RD bit BACK: SZ IAR1.0...

  • Page 50: Oscillator

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator...

  • Page 51: External Crystal/Ceramic Oscillator - Hxt

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Hi�h Speed Oscillation (HOSC) /� /� Prescaler /3� HIRC Fast Wake-�p from SLEEP Mode or Hi�h Speed Oscillation IDLE Mode Control (for HXT only) Confi��ration Option CKS[�:0]� HLCLK LIRC Low Speed Prescaler Time Base...

  • Page 52: External Rc Oscillator - Erc

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Crystal Oscillator C1 and C2 Values Crystal Frequency 1�MHz �MHz 4MHz 1MHz 100pF 100pF Note: C1 and C� val�es are for ��idance only. Crystal Recommended Capacitor Values External RC Oscillator – ERC Using the ERC oscillator only requires that a resistor, with a value between 56k and 2.4M , is Ω...

  • Page 53: External 3�.�6�Khz Crystal Oscillator - Lxt

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. The external parallel feedback resistor, Rp, is required. Some configuration options determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins.

  • Page 54: Internal Low Speed Oscillator - Lirc

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the SMOD2 register. • SMOD2 Register Name — — — — — — — LXTLP — — — — — — — — — — — — — — Bit 7~1 Unimplemented, read as "0"...

  • Page 55: Operating Modes And System Clocks

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clock The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, f , or low frequency, f , source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from an HXT, ERC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from the clock, f . If f is selected then it can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of /2~f /64. The f clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. The f clock is also used to provide the clock source for time base and watchdog timer functions.

  • Page 56: System Operation Modes

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,...
  • Page 57 HT66F60A/HT66F70A A/D Flash MCU with EEPROM IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the SMOD1 register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the f clock will also be on. Control Register A register pair, SMOD and SMOD1, is used for overall control of the internal clocks within the device. SMOD Register Name CKS� CKS1 CKS0 FSTEN IDLEN HLCLK Bit 7~5 CKS2~CKS0: The system clock selection when HLCLK is "0" 000: f or f LIRC 001: f or f SUB LIRC 010: f 011: f 100: f...
  • Page 58 HT66F60A/HT66F70A A/D Flash MCU with EEPROM HTO: High speed system oscillator ready flag Bit 2 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used or 15~16 clock cycles if the ERC or HIRC oscillator is used. bit 1 IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. bit 0 HLCLK: system clock selection 0: f /2~f /64 or f 1: f This bit is used to select if the f...
  • Page 59 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SMOD1 Register Name FSYSON — — — — LVRF — — — — — — — — “x”: �nknown Bit 7 FSYSON: f Control in IDLE Mode 0: Disable 1: Enable Bit 6~3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific Low Voltage Reset situation occurs. This bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR Control register software reset flag...

  • Page 60: Fast Wake-�P

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows f , namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is f the Fast Wake-up function is only available in the SLEEP1 and SUB, IDLE0 modes. When the device is woken up from the SLEEP0 mode, the FastWake-up function has no effect because the f clock is stopped. The FastWake-up enable/disable function is controlled using the FSTEN bit in the SMOD1 register. If the HXT oscillator is selected as the NORMAL Mode system clock and if the Fast Wake-up function is enabled, then it will take one to two t clock cycles of the LXT or LIRC oscillator for the system to wake-up. The system will then initially run under the f clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC/HIRC or LIRC oscillator is used as the system oscillator, then it will take15~16 clock cycles of the ERC/HIRC oscillator or 1~2 clock cycles of the LIRC osrillator respectively to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Wake-up Time Wake-up Time Wake-up Time...

  • Page 61: Operatin� Mode Switchin

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the SMOD1 register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, f , to the clock source, f /2~f /64 or f . If the clock is from the f , the high speed clock source will stop running to conserve power. When this happens it must be noted...
  • Page 62 HT66F60A/HT66F70A A/D Flash MCU with EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. N O R M A L M o d e C K S 2 ~ C K S 0 = 0 0 x B &...

  • Page 63: Slow Mode To Norm�L Mode Switchin

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. S L O W M o d e C K S 2 ~ C K S 0 ¹ 0 0 0 B , 0 0 1 B a s H L C L K = 0...

  • Page 64: Enterin� The Sleep0 Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and the f clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped as the WDT is disabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT”...

  • Page 65: Enterin� The Idle1 Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in SMOD1 register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and f clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting as the WDT clock source is derived from the f SUB clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on these devices. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.

  • Page 66: Wake-�P

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, these devices will experience a full system reset, however, if these devices are woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt...

  • Page 67: Watchdog Timer

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the f clock. The f clock can be sourced from either the LXT or LIRC oscillator selected by a configuration option. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with V temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register controls the overall operation of the Watchdog Timer.

  • Page 68: Watchdo� Timer Operation

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM SMOD1 Register Name FSYSON — — — — LVRF — — — — — — — — “x”: �nknown Bit 7 FSYSON: f Control in IDLE Mode Described elsewhere Bit 6~3 Unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag Described elsewhere Bit 1 LRF: LVR Control register software reset flag Described elsewhere WRF: WDT Control register software reset flag bit 0 0: Not occurred...
  • Page 69 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT contents. The maximum time out period is when the 2 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 division ratio, and a minimum timeout of 7.8ms for the 2 division ration. WDTC Re�ister WE4~WE0 bits Reset MCU “CLR WDT”Instr�ction � /� �-sta�e Divider WDT Prescaler LIRC Low Speed Oscillator WS�~WS0 �-to-1 MUX...

  • Page 70: Reset And Initialisation

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the is running. One example of this is where after power has been applied and the is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both...
  • Page 71 HT66F60A/HT66F70A A/D Flash MCU with EEPROM RES Pin As the reset pin is shared with PB.0, the reset function must be selected using a configuration option. Although the microcontroller has an internal RC reset function, if the V power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time t is invoked to provide an extra delay time after which the RSTD microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
  • Page 72 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, V . If the supply voltage of the device drops to within a range of 0.9V~V such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the SMOD1 register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~V must exist for a time greater than that specified by t in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual V value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 f clock cycles. When this happens, the LRF bit in the SMOD1 register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. L V R R S T D + S S T...
  • Page 73 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • SMOD1 Register Name FSYSON — — — — LVRF — — — — — — — — “x”: �nknown FSYSON: f Bit 7 Control in IDLE Mode Described elsewhere Bit 6~3 Unimplemented, read as "0" LVRF: LVR function reset flag Bit 2 0: Not occurred 1: Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. LRF: LVR Control register software reset flag Bit 1...

  • Page 74: Reset Initial Conditions

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: RESET Conditions Power-on reset � � RES or LVR reset d�rin� NORM�L or SLOW Mode operation �...
  • Page 75 HT66F60A/HT66F70A A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) P�WU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 �...
  • Page 76 HT66F60A/HT66F70A A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) TM1C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 �...
  • Page 77 HT66F60A/HT66F70A A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) SIMC�/ ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 �...

  • Page 78: Input/Output Ports

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM WDT Time-out WDT Time-out Register Power-on Reset RES or LVR Reset (Normal Operation) (HALT) P�S� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 �...
  • Page 79 HT66F60A/HT66F70A A/D Flash MCU with EEPROM I/O Port Register List Register Name P�WU P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU� P�WU1 P�WU0 P�PU P�PU� P�PU6 P�PU5 P�PU4 P�PU3 P�PU� P�PU1 P�PU0 P� P�� P�6 P�5 P�4 P�3 P�� P�1 P�0 P�C P�C�...
  • Page 80 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PHPU, and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Name P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU�...
  • Page 81 HT66F60A/HT66F70A A/D Flash MCU with EEPROM select the functions of the pin-shared function pins. When the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. For example, if the I C SDA line is used, the corresponding output pin-shared function should be configured as the SDI/SDA function by configuring the PxSn register and the SDA signal intput should be properly selected using the IFSi register. However, if the external interrupt function is selected to be used, the relevant output...
  • Page 82 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PAS0 Name P�1S3 P�1S� P�1S1 P�1S0 D� Bit 7~4 PA1S3~PA1S0: Port A1 Function Selection 0000: I/O 0001: TP1A 0011: AN1 Others: Reserved Bit 3~0 Reserved bits, can be read and written • PAS1 Name P�3S3 P�3S� P�3S1 P�3S0 D� PA3S3~PA3S0: Port A3 Function Selection Bit 7~4 0000: I/O 0011: AN3 0111: C0N 1111: AN3 and C0N Others: Reserved Bit 3~0 Reserved bits, can be read and written • PAS2 Name P�5S3...
  • Page 83 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PAS3 Name P��S3 P��S� P��S1 P��S0 P�6S3 P�6S� P�6S1 P�6S0 Bit 7~4 PA7S3~PA7S0: Port A7 Function Selection 0000: I/O 0010: SCK/SCL 0011: AN7 Others: Reserved Bit 3~0 PA6S3~PA6S0: Port A6 Function Selection 0000: I/O 0010: SDI/SDA 0011: AN6 Others: Reserved • PBS2 Name PB5S3 PB5S� PB5S1 PB5S0 D� Bit 7~4 PB5S3~PB5S0: Port B5 Function Selection 0000: I/O...
  • Page 84 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PCS0 Name PC1S3 PC1S� PC1S1 PC1S0 PC0S3 PC0S� PC0S1 PC0S0 Bit 7~4 PC1S3~PC1S0: Port C1 Function Selection 0000: I/O 0001: TP1B 0010: TP1BB 0011: SCOM1 Others: Reserved PC0S3~PC0S0: Port C0 Function Selection Bit 3~0 0000: I/O 0001: TP1B 0010: TP1BB 0011: SCOM0 Others: Reserved • PCS1 Name PC3S3 PC3S� PC3S1 PC3S0 PC�S3 PC�S�...
  • Page 85 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PCS3 Name PC�S3 PC�S� PC�S1 PC�S0 PC6S3 PC6S� PC6S1 PC6S0 Bit 7~4 PC7S3~PC7S0: Port C7 Function Selection 0000: I/O 0001: TP1A 0011: SCOM3 Others: Reserved Bit 3~0 PC6S3~PC6S0: Port C6 Function Selection 0000: I/O 0001: TP0 0010: TP0B 0011: SCOM2 Others: Reserved • PDS0 Name PD1S3 PD1S� PD1S1 PD1S0 PD0S3 PD0S� PD0S1...
  • Page 86 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PDS2 Name PD5S3 PD5S� PD5S1 PD5S0 PD4S3 PD4S� PD4S1 PD4S0 Bit 7~4 PD5S3~PD5S0: Port D5 Function Selection 0000: I/O 0001: TP0 0010: TP0B Others: Reserved Bit 3~0 PD4S3~PD4S0: Port D4 Function Selection 0000: I/O 0001: TP2 0010: TP2B Others: Reserved • PDS3 Name PD�S3 PD�S� PD�S1 PD�S0 PD6S3 PD6S� PD6S1 PD6S0...
  • Page 87 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PES1 Name PE3S3 PE3S� PE3S1 PE3S0 D� Bit 7~4 PE3S3~PE3S0: Port E3 Function Selection 0000: I/O 0001: SDOA Others: Reserved Bit 3~0 Reserved bits, can be read and written. • PES2 Name PE5S3 PE5S� PE5S1 PE5S0 PE4S3 PE4S� PE4S1 PE4S0 Bit 7~4 PE5S3~PE5S0: Port E5 Function Selection 0000: I/O 0001: TP3 0010: TP3B Others: Reserved PE4S3~PE4S0: Port E4 Function Selection Bit 3~0...
  • Page 88 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PFS0 Name PF1S3 PF1S� PF1S1 PF1S0 PF0S3 PF0S� PF0S1 PF0S0 Bit 7~4 PF1S3~PF1S0: Port F1 Function Selection 0000: I/O 0011: AN11 0111: C1P 1111: AN11 and C1P Others: Reserved PF0S3~PF0S0: Port F0 Function Selection Bit 3~0 0000: I/O 0011: AN10 0111:C1N 1111: AN10 and C1N Others: Reserved • PGS0 Name PG1S3 PG1S� PG1S1 PG1S0 PG0S3 PG0S�...
  • Page 89 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PGS2 Name D� PG4S3 PG4S� PG4S1 PG4S0 Bit 7~4 Reserved bits, can be read and written. Bit 3~0 PG4S3~PG4S0: Port G4 Function Selection 0000: I/O 0001: TP4 0010: TP4B Others: Reserved • PGS3 Name PG�S3 PG�S� PG�S1 PG�S0 PG6S3 PG6S� PG6S1 PG6S0 Bit 7~4 PG7S3~PG7S0: Port G7 Function Selection 0000: I/O 0001: TP5 0010: TP5B Others: Reserved Bit 3~0...
  • Page 90 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • PHS1 Name PH3S3 PH3S� PH3S1 PH3S0 PH�S3 PH�S� PH�S1 PH�S0 Bit 7~4 PH3S3~PH3S0: Port H3 Function Selection 0000: I/O 0001: SCKA Others: Reserved PH2S3~PH2S0: Port H2 Function Selection Bit 3~0 0000: I/O 0001: SCSA Others: Reserved • PHS2 Name PH5S3 PH5S� PH5S1 PH5S0 D� Bit 7~4 PH5S3~PH5S0: Port H5 Function Selection 0000: I/O 0001: SDOA Others: Reserved Bit 3~0 Reserved bits, can be read and written.
  • Page 91 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • IFS1 Name TCK3S1 TCK3S0 TCK�S1 TCK�S0 TCK1S1 TCK1S0 TCK0S1 TCK0S0 Bit 7~6 TCK3S1~TCK3S0: TCK3 input source pin selection 00: PC4 Others: PE3 Bit 5~4 TCK2S1~TCK2S0: TCK2 input source pin selection 00: PC2 Others: PD0 Bit 3~2 TCK1S1~TCK1S0: TCK1 input source pin selection 00: PA4 Others: PD3 Bit 1~0 TCK0S1~TCK0S0: TCK0 input source pin selection 00: PH1 Others: PD2 • IFS2 Name TP�IS1 TP�IS0 TP1IBS1 TP1IBS0 TP1I�S1 TP1I�S0...
  • Page 92 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • IFS4 Name D� SDIS1 SDIS0 SCKS1 SCKS0 SCSBS1 SCSBS0 Bit 7~6 Reserved bits, can be read and written. Bit 5~4 SDIS1~SDIS0: SDI/SDA input source pin selection 00: PA6 01: PB7 Others: PD2 SCKS1~SCKS0: SCK/SCL input source pin selection Bit 3~2 00: PA7 01: PD3 10: PD1 11: PD6 SCSBS1~SCSBS0: SCS input source pin selection Bit 1~0 00: PB5 01: PD0 Others: PD7 • IFS5 Name D� SDI�S1 SDI�S0 SCK�S1 SCK�S0 SCS�BS1 SCS�BS0...

  • Page 93: I/O Pin Str�Ct�Res

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. P u l l - H i g h R e g i s t e r C o n t r o l B i t...

  • Page 94: Pro�Rammin� Considerations

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has...

  • Page 95: Tm Operation

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM unit which are shown in the table together with their individual reference name, TM0~TM5. Device HT66F60� 10-bit CTM 10-bit ETM 16-bit STM 10-bit CTM 16-bit STM 16-bit STM HT66F�0� TM Name/Type Reference TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TMn control registers. The clock source can be a ratio of either the system clock f...

  • Page 96: Tm External Pins

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM TM External Pins Each of the TMs, irrespective of what type, has two TM input pins, with the label TCKn and TPnI respectively. The TM input pin, TCKn, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TCKn pin is also used as the external trigger input pin in single pulse mode for the STM and ETM. The other TM input pin, TPnI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The TMs each have one or more output pins with the label TPn and TPnB respectively. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. The corresponding selection bits in the pin-shared function registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. Device Registers TP�� TP�B� TP�I� TCK� HT66F60� TP0� TP0B� TCK0 TP1�� TP1I�� TCK1 TP4�...

  • Page 97: Tm Inp�T/O�Tp�T Pin Control

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM TM Input/Output Pin Control Selecting to have a TM input/output or whether to retain its other shared function is implemented using one or two registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. TCKn (TMn) CCR o�tp�t TPnB CCR inverted o�tp�t CTM Function Pin Control Block Diagram (n=0 or 3)
  • Page 98 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. TM Co�nter Re�ister (Read only) TMxDL TMxDH �-bit B�ffer TMx�L TMx�H TM CCR� Re�ister (Read/Write) TMxBL TMxBH TM CCRB Re�ister (Read/Write) Data B�s As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers...

  • Page 99: Compact Type Tm - Ctm

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Compact Type TM – CTM Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. Device TM Type TM Name TM Input Pin TM Output Pin HT66F60� 10-bit CTM TM0� TM3 TCK0� TP0I; TCK3� TP3I TP0� TP0B; TP3� TP3B HT66F�0�...

  • Page 100: Compact Type Tm Re�Ister Description

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON TnRP�...
  • Page 101 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TMnC0 Register Name TnP�U TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0 TnPAU: TMn Counter Pause Control Bit 7 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TM0 Counter clock 000: f 001: f 010: f 011: f 100: f 101: Reserved 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f is the...
  • Page 102 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Bit 2~0 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
  • Page 103 HT66F60A/HT66F70A A/D Flash MCU with EEPROM In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off.

  • Page 104: Compact Type Tm Operatin� Modes

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to “00” respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the...
  • Page 105 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e Co�nter overflow TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCR� Time TnON TnP�U TnPOL CCRP Int.
  • Page 106 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflow 0x3FF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U TnPOL No Tn�F fla�...

  • Page 107: Timer/Co�Nter Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM...
  • Page 108 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns hi�h CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCR� Time TnON TnP�U TnPOL CCR� Int.
  • Page 109 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stop if Pa�se Res�me TnON bit low CCRP Time TnON TnP�U TnPOL CCRP Int.

  • Page 110: Standard Type Tm - Stm

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. Device TM Type TM Name TM Input Pin TM Output Pin TCK�� TP�I; TP�� TP�B;...

  • Page 111: Standard Type Tm Re�Ister Description

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON — —...
  • Page 112 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TnON: TMn Counter On/Off Control Bit 3 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0 Unimplemented, read as “0” TMnC1 Register Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR Bit 7~6 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
  • Page 113 HT66F60A/HT66F70A A/D Flash MCU with EEPROM In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only after the TM has been switched off. Unpredictable...
  • Page 114 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TMnDL Register Name D� D� Bit 7~0 TMnDL: TMn Counter Low Byte Register bit 7~bit 0 TMn 16-bit Counter bit 7~bit 0 TMnDH Register Name D1� D� Bit 7~0 TMnDH: TMn Counter High Byte Register bit 7~bit 0 TMn 16-bit Counter bit 15~bit 8 TMnAL Register Name D� D� TMnAL: TMn CCRA Low Byte Register bit 7~bit 0 Bit 7~0 TMn 16-bit CCRA bit 7~bit 0 TMnAH Register Name D1� D� TMnAH: TMn CCRA High Byte Register bit 7~bit 0 Bit 7~0 TMn 16-bit CCRA bit 15~bit 8 TMnRP Register Name D�...

  • Page 115: Standard Type Tm Operatin� Modes

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0...
  • Page 116 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TnCCLR = 0; TnM[1:0] = 00 Co�nter Co�nter Val�e overflow CCRP = 0 CCRP > 0 Co�nter cleared by CCRP val�e 0xFFFF CCRP > 0 CCRP Pa�se Res�me Co�nter Stop Reset CCR� Time TnON bit TnP�U bit...
  • Page 117 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TnCCLR = 1; TnM[1:0] = 00 Co�nter Val�e CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflows 0xFFFF CCR� = 0 CCR� Pa�se Res�me Co�nter Stop Reset CCRP Time TnON bit TnP�U bit...

  • Page 118: Timer/Co�Nter Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle...
  • Page 119 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 0; TnM [1:0] = 10 Co�nter cleared by CCRP Co�nter Reset when TnON ret�rns hi�h CCRP Co�nter Stop if Pa�se Res�me TnON bit low CCR� Time TnON TnP�U TnPOL CCR� Int.
  • Page 120 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnDPX = 1; TnM [1:0] = 10 Co�nter cleared by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stop if Pa�se Res�me TnON bit low CCRP Time TnON TnP�U TnPOL CCRP Int.

  • Page 121: Sin�Le P�Lse Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. L e a d i n g E d g e T r a i l i n g E d g e...
  • Page 122 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnM [1:0] = 10 ; TnIO [1:0] = 11 Co�nter stopped by CCR� Co�nter Reset when TnON ret�rns hi�h CCR� Co�nter Stops Res�me Pa�se by software CCRP Time TnON ��to. set by...
  • Page 123 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnI pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPnI pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPnI pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPnI pin, however it must be noted that the counter will continue to run.
  • Page 124 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Counter Value TnM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP Resume Pause Time TnON TnPAU Active Active Active edge edge edge TM capture pin TPnI CCRA Int. Flag TnAF CCRP Int.

  • Page 125: Enhanced Type Tm - Etm

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Enhanced Type TM – ETM The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. Device TM Type TM Name. TM Input Pin TM Output Pin HT66F60� 10-bit ETM TCK1;...
  • Page 126 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM1C0 T1P�U TnCK� TnCK1 TnCK0 TnON T1RP� T1RP1...
  • Page 127 HT66F60A/HT66F70A A/D Flash MCU with EEPROM T1ON: TM1 Counter On/Off Control Bit 3 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run and clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks...
  • Page 128 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TM1C1 Register Name T1�M1 T1�M0 T1�IO1 T1�IO0 T1�OC T1�POL T1CDN T1CCLR T1AM1~T1AM0: Select TM1 CCRA Operating Mode Bit 7~6 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T1AIO1~T1AIO0: Select TP1A output function...
  • Page 129 HT66F60A/HT66F70A A/D Flash MCU with EEPROM T1AOC: TP1A Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter...
  • Page 130 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TM1C2 Register Name T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0 T1BM1~T1BM0: Select TM1 CCRB Operating Mode Bit 7~6 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T1BIO1~T1BIO0: Select TP1B, TP1BB output function...
  • Page 131 HT66F60A/HT66F70A A/D Flash MCU with EEPROM T1BOC: TP1B, TP1BB Output control bit Bit 3 Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter...
  • Page 132 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TM1AH Register Name — — — — — — D� — — — — — — — — — — — — Bit 7~2 Unimplemented, read as "0" Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 TM1BL Register Name D� D� Bit 7~0 TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0...

  • Page 133: Compare O�Tp�T Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TP1B, TP1BB pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TP1B, TP1BB output pins. Note that if the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place. Rev. 1.40 ����st ��� �01�...
  • Page 134 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; Tn�M [1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCR� Time TnON TnP�U Tn�POL...
  • Page 135 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter overflow Co�nter Val�e TnCCLR = 0; TnBM [1:0] = 00 CCRP > 0 CCRP=0 Co�nter cleared by CCRP val�e 0x3FF CCRP > 0 Co�nter Res�me Restart CCRP Pa�se Stop CCRB Time TnON TnP�U TnBPOL CCRP Int.
  • Page 136 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; Tn�M [1:0] = 00 CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflow 0x3FF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRP Time TnON TnP�U Tn�POL...
  • Page 137 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; TnBM [1:0] = 00 CCR� = 0 CCR� > 0 Co�nter cleared by CCR� val�e Co�nter overflow 0x3FF CCR�=0 Res�me CCR� Pa�se Stop Co�nter Restart CCRB Time TnON TnP�U TnBPOL No Tn�F fla�...

  • Page 138: Timer/Co�Nter Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
  • Page 139 HT66F60A/HT66F70A A/D Flash MCU with EEPROM ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 1�� �56 3�4 51� �6� �96 10�4 � D�ty CCR� B D�ty CCRB If f =12MHz, TM clock source select f /4, CCRP=100b, CCRA=128 and CCRB=256, The TPnA PWM output frequency=(f /4)/512=f /2048=5.8594kHz, duty=128/512=25%.
  • Page 140 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 0; Co�nter Cleared by CCRP Tn�M [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 00 CCRP CCR� Co�nter Res�me Stop Pa�se Restart CCRB Time TnON TnP�U Tn�POL CCR� Int.
  • Page 141 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Counter Value TnCCLR = 1; TnBM [1:0] = 10; Counter Cleared by CCRA TnPWM [1:0] = 00 CCRA Counter Resume Stop Pause Restart CCRB Time TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int.
  • Page 142 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 0; Tn�M [1:0] = 10� TnBM [1:0] = 10; TnPWM [1:0] = 11 CCRP Co�nter Stop Restart Res�me CCR� Pa�se CCRB Time TnON TnP�U Tn�POL CCR� Int. Fla� Tn�F CCRB Int.
  • Page 143 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 11 CCR� Co�nter Stop Restart Res�me Pa�se CCRB Time TnON TnP�U TnBPOL CCR� Int. Fla� Tn�F CCRB Int. Fla� TnBF CCRP Int.

  • Page 144: Sin�Le P�Lse Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB or TPnBB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB or TPnBB. In this way the CCRA value can be used to control the pulse width of TPnA. The (CCRA-CCRB) value can be used to control the pulse width of TPnB and TPnBB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Co�nter Val�e CCR�...
  • Page 145 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Co�nter Val�e Tn�M [1:0] = 10� TnBM [1:0] = 10; Co�nter stopped Tn�IO [1:0] = 11� TnBIO [1:0] = 11 by CCR� Co�nter Reset CCR� when TnON ret�rns hi�h Co�nter Stops Res�me Pa�se by software...

  • Page 146: Capt�Re Inp�T Mode

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnIA and TPnIB pins, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnIA and TPnIB pins, the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated.
  • Page 147 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Counter Value TnAM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP Resume Pause Time TnON TnPAU Active Active Active edge edge edge TM capture pin TPnIA CCRA Int. Flag TnAF CCRP Int.
  • Page 148 HT66F60A/HT66F70A A/D Flash MCU with EEPROM TnBM1, TnBM0 = 01 Counter Counter Value overflow CCRP Counter Stop Reset Pause Resume Time TnON bit TnPAU bit Active Active Active edges TM Capture edge edge Pin TPnIB CCRB Int. Flag TnBF CCRP Int.

  • Page 149: Aanlog To Digital Converter

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Aanlog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. Part No. Input Channels A/D Channel Select Bits Input Pins HT66F60�...
  • Page 150 HT66F60A/HT66F70A A/D Flash MCU with EEPROM A/D Converter Data Registers – ADRL, ADRH As the devices contain an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRH ADRL ADRFS D11 D10 D9 D�...
  • Page 151 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • ADCR0 Register Name ST�RT EOCB �DOFF �CS4 �CS3 �CS� �CS1 �CS0 Bit 7 START: Start the A/D conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running, the bit will be high. Bit 5 ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications.
  • Page 152 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • ADCR1 Register Name — VBGEN �DRFS VREFS — �DCK� �DCK1 �DCK0 — — — — Bit 7 Unimplemented, read as “0” Bit 6 VBGEN: Internal Bandgap voltage control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When 1.25V is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion.

  • Page 153: D Operation

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to “0” by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set...

  • Page 154: D Inp�T Pins

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A, Port E, Port F and Port H as well as other functions. The corresponding selection bits in the PAS0~PAS3, PES3, PFS0 and PHS0 registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the corresponding pin is setup to be an A/D converter input, the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC, PEC, PFC or PHC port control register to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of V P H 0 / A N P F 1 / A N 1 1 1 .
  • Page 155 HT66F60A/HT66F70A A/D Flash MCU with EEPROM • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data register ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16t where t is equal to the A/D clock period.

  • Page 156: Pro�Rammin� Considerations

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the V or V voltage, this gives a single bit analog input value of V or V divided by 4096. 1 LSB=(V or V )÷4096...
  • Page 157 HT66F60A/HT66F70A A/D Flash MCU with EEPROM A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select f /8 as A/D clock and switch off 1.25V clr ADOFF mov a,03h ; setup PHS0 to configure pin AN0...
  • Page 158 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select f /8 as A/D clock and switch off 1.25V clr ADOFF mov a,03h ; setup PHS0 to configure pin AN0 mov PHS0,a mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter...

  • Page 159: Comparators

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Comparators Two independent analog comparators are contained within these devices. These functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused. C n P O L C n O U T C n + C n X C n - P i n - s h a r e d f u n c t i o n...

  • Page 160: Comparator Re�Isters

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Comparator Registers There are two registers for overall comparator operation, one for each comparator. As corresponding bits in the two registers have identical functions, they following register table applies to both registers. Register Name CP0C — C0EN C0POL C0OUT — — — C0HYEN CP1C — C1EN C1POL C1OUT —...
  • Page 161 HT66F60A/HT66F70A A/D Flash MCU with EEPROM CP1C Register Name — C1EN C1POL C1OUT — — — C1HYEN — — — — — — — — Bit 7 Unimplemented, read as "0" Bit 6 C1EN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the SLEEP or IDLE mode. Bit 5 C1POL: Comparator output polarity 0: Output not inverted 1: Output inverted This is the comparator polarity bit. If the bit is zero then the C1OUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator...

  • Page 162: Comparator Interr�Pt

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Comparator Interrupt Each also possesses its own interrupt function. When any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the C0OUT or C1OUT bit and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four-line SPI interface or two-line I C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using...
  • Page 163 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. S P I M a s t e r...

  • Page 164: Spi Re�Isters

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I C interface. Register Name SIMC0 SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN — SIMD D� D� SIMC� D� CKPOLB CKEG CSEN WCOL SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the devices write data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the devices can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register.
  • Page 165 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SIMC0 Register Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN — — — — — SIM2, SIM1, SIM0: SIM Operating Mode Control Bit 7~5 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f 010: SPI master mode; SPI clock is f 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master devices.
  • Page 166 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SIMC2 Register Name D� CKPOLB CKEG CSEN WCOL Bit 7~6 Undefined bit This bit can be read or written by the application program. Bit 5 CKPOLB: Determines the base condition of the clock line 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3...

  • Page 167: Spi Comm�Nication

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. S I M E N = 1 , C S E N = 0 ( E x t e r n a l P u l l - H i g h )
  • Page 168 HT66F60A/HT66F70A A/D Flash MCU with EEPROM S C S S C K ( C K P O L B = 1 ) S C K ( C K P O L B = 0 ) S D O D 7 / D 0...

  • Page 169: I C Interface

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. V D D S D A S C L D e v i c e...
  • Page 170 HT66F60A/HT66F70A A/D Flash MCU with EEPROM S T A R T s i g n a l f r o m M a s t e r S e n d s l a v e a d d r e s s...
  • Page 171 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SIMC0 Register Name SIM� SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN — — — — — SIM2, SIM1, SIM0: SIM Operating Mode Control Bit 7~5 000: SPI master mode; SPI clock is f 001: SPI master mode; SPI clock is f 010: SPI master mode; SPI clock is f 011: SPI master mode; SPI clock is f 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device.
  • Page 172 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SIMC1 Register Name H��S TX�K I�MWU RX�K HCF: I Bit 7 C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave...
  • Page 173 HT66F60A/HT66F70A A/D Flash MCU with EEPROM RXAK: I Bit 0 C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I C functions. Before the devices write data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the devices can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Name D� D� “x”: �nknown SIMA Register Name IIC�6 IIC�5 IIC�4 IIC�3 IIC��...
  • Page 174 HT66F60A/HT66F70A A/D Flash MCU with EEPROM D a t a B u s C D a t a R e g i s t e r S l a v e A d d r e s s R e g i s t e r...

  • Page 175: Slave �Ddress

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM S t a r t S E T S I M [ 2 : 0 ] = 1 1 0 S E T S I M E N W r i t e S l a v e...
  • Page 176 HT66F60A/HT66F70A A/D Flash MCU with EEPROM C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the C bus or write data to the I C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes to read data from the I C bus, therefore the slave device must be setup to send data to the I C bus as a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I bus, therefore the slave device must be setup to read data from the I C bus as a receiver. C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The...
  • Page 177 HT66F60A/HT66F70A A/D Flash MCU with EEPROM S t a r t S l a v e A d d r e s s S R W A C K S C L S D A D a t a A C K...
  • Page 178 HT66F60A/HT66F70A A/D Flash MCU with EEPROM C Time-out Control In order to reduce the I C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I C bus is not received for a while, then the C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I C bus “START” & “address match”condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the I2CTOC register, then a time-out condition will occur. The time-out function will stop when an I C “STOP” condition occurs. S t a r t S l a v e A d d r e s s S R W...

  • Page 179: Peripheral Clock Output

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM I2CTOC Register Name I�CTOEN I�CTOF I�CTOS5 I�CTOS4 I�CTOS3 I�CTOS� I�CTOS1 I�CTOS0 I2CTOEN: I Bit 7 C Time-out Control 0: Disable 1: Enable I2CTOF: I Bit 6 C Time-out flag 0: No time-out occurred 1: Time-out occurred I2CTOS5~I2CTOS0: I Bit 5~0 C Time-out Time Selection C Time-out clock source is f C Time-out time is given by: (I2CTOS [5:0] +1) × (32/f Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen using the relevant pin-shared function selection bit. The Peripheral Clock function is controlled...
  • Page 180 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Peripheral Clock Registers There are two internal registers which control the overall operation of the Peripheral Clock Output. These are the PSC1 and TBC2 registers. Name PSC1 — — — — — — CLKS11 CLKS10 TBC� TB�EN — — — — TB�� TB�1 TB�0 PCK Register List PSC1 Register Name — — — —...

  • Page 181: Serial Interface - Spia

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Serial Interface – SPIA The device contains an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. This SPIA interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, this device is provided only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA...
  • Page 182 HT66F60A/HT66F70A A/D Flash MCU with EEPROM D a t a B u s S P I A D S P I A P i n T x / R x S h i f t R e g i s t e r...
  • Page 183 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPIAD Register Name D� D� × × × × × × × × “×” �nknown There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag, etc. SPIAC0 Register Name S�SPI� S�SPI1 S�SPI0 — — — SPI�EN —...
  • Page 184 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPIAC1 Register Name — — S�CKPOL S�CKEG S�MLS S�CSEN S�WCOL S�TRF — — — — Bit 7~6 Unimplemented, read as “0” Bit 5 SACKPOL: Determines the base condition of the clock line 0: SCKA line will be high when the clock is inactive 1: SCKA line will be low when the clock is inactive The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. Bit 4 SACKEG: Determines the SPIA SCKA active clock edge type SACKPOL=0: 0: SCKA has high base level with data capture on SCKA rising edge 1: SCKA has high base level with data capture on SCKA falling edge SACKPOL=1: 0: SCKA has low base level with data capture on SCKA falling edge 1: SCKA has low base level with data capture on SCKA rising edge The SACKEG and SACKPOL bits are used to setup the way that the clock signal outputs and inputs data on the SPIA bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The...
  • Page 185 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD registers. The master should output a SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOL bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCSA signal for various configurations of the SACKPOL and SACKEG bits. The SPIA will continue to function even in the IDLE Mode. S P I A t r a n s f e r W r i t e D a t a...
  • Page 186 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPI� master mode SPI�EN = 1� S�CSEN= 0 ( external p�ll- hi�h ) SCS� SPI�EN = 1� S�CSEN= 1 SCK� ( S�CKPOL= 1� S�CKEG = 0 ) SCK� ( =0 ) S�CKPOL =0� S�CKEG SCK�...
  • Page 187 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SPIA Bus Enable/Disable To enable the SPIA bus, set SACSEN=1 and SCSA=0, then wait for data to be written into the SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in. To Disable the SPIA bus SCKA, SDIA, SDOA, SCSA will become I/O pins or other pin-shared functions. SPIA Operation All communication is carried out using the 4-line interface for either Master or Slave Mode. The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be an I/O pin or other pin-shared functions and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master Mode the SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOL in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA pins will all become I/O pins or other pin-shared functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode: • Step 1 Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this must be same as the Slave device.

  • Page 188: Error Detection

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Slave Mode: • Step 1 Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this setting must be the same with the Master device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt.

  • Page 189: Interrupts

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT3 and PINT pins, while the internal interrupts are generated by various internal functions such as the TMs, Comparators,Time Base, LVD, EEPROM, SIM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain...
  • Page 190 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Interrupt Register Contents Name INTEG INT3EG1 INT3EG0 INT�EG1 INT�EG0 INT1EG1 INT1EG0 INT0EG1 INT0EG0 INTC0 — CP0F INT1F INT0F CP0E INT1E INT0E INTC1 �DF MF1F MF0F CP1F �DE MF1E MF0E CP1E INTC� MF3F TB1F TB0F MF�F...
  • Page 191 HT66F60A/HT66F70A A/D Flash MCU with EEPROM INTC0 Register Name — CP0F INT1F INT0F CP0E INT1E INT0E — — Bit 7 Unimplemented, read as “0” Bit 6 CP0F: Comparator 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request INT0F: INT0 interrupt request flag Bit 4 0: No request 1: Interrupt request CP0E: Comparator 0 interrupt control Bit 3 0: Disable 1: Enable INT1E: INT1 interrupt control Bit 2 0: Disable 1: Enable...
  • Page 192 HT66F60A/HT66F70A A/D Flash MCU with EEPROM INTC1 Register Name �DF MF1F MF0F CP1F �DE MF1E MF0E CP1E ADF: A/D Converter interrupt request flag Bit 7 0: No request 1: Interrupt request MF1F: Multi-function interrupt 1 request flag Bit 6 0: No request 1: Interrupt request MF0F: Multi-function interrupt 0 request flag Bit 5 0: No request 1: Interrupt request CP1F: Comparator 1 interrupt request flag Bit 4 0: No request 1: Interrupt request ADE: A/D Converter interrupt control Bit 3 0: Disable 1: Enable MF1E: Multi-function interrupt 1 control Bit 2 0: Disable...
  • Page 193 HT66F60A/HT66F70A A/D Flash MCU with EEPROM INTC2 Register Name MF3F TB1F TB0F MF�F MF3E TB1E TB0E MF�E MF3F: Multi-function interrupt 3 request flag Bit 7 0: No request 1: Interrupt request TB1F: Time Base 1 interrupt request flag Bit 6 0: No request 1: Interrupt request TB0F: Time Base 0 interrupt request flag Bit 5 0: No request 1: Interrupt request MF2F: Multi-function interrupt 2 request flag Bit 4 0: No request 1: Interrupt request MF3E: Multi-function interrupt 3 control Bit 3 0: Disable 1: Enable TB1E: Time Base 1 interrupt control Bit 2 0: Disable...
  • Page 194 HT66F60A/HT66F70A A/D Flash MCU with EEPROM INTC3 Register Name — MF4F INT3F INT�F — MF4E INT3E INT�E — — Bit 7 Unimplemented, read as “0” Bit 6 MF4F: Multi-function interrupt 4 request flag 0: No request 1: Interrupt request Bit 5 INT3F: INT3 interrupt request flag 0: No request 1: Interrupt request INT2F: INT2 interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” MF4E: Multi-function interrupt 4 control Bit 2 0: Disable 1: Enable INT3E: INT3 interrupt control...
  • Page 195 HT66F60A/HT66F70A A/D Flash MCU with EEPROM MFI0 Register Name T��F T�PF T0�F T0PF T��E T�PE T0�E T0PE T2AF: TM2 Comparator A match interrupt request flag Bit 7 0: No request 1: Interrupt request T2PF: TM2 Comparator P match interrupt request flag Bit 6 0: No request 1: Interrupt request T0AF: TM0 Comparator A match interrupt request flag Bit 5 0: No request 1: Interrupt request T0PF: TM0 Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request T2AE: TM2 Comparator A match interrupt control Bit 3 0: Disable 1: Enable T2PE: TM2 Comparator P match interrupt control Bit 2 0: Disable...
  • Page 196 HT66F60A/HT66F70A A/D Flash MCU with EEPROM MFI1 Register Name — T1BF T1�F T1PF — T1BE T1�E T1PE — — — — Bit 7 Unimplemented, read as “0” Bit 6 T1BF: TM1 Comparator B match interrupt request flag 0: No request 1: Interrupt request Bit 5 T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request T1PF: TM1 Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” T1BE: TM1 Comparator B match interrupt control Bit 2 0: Disable...
  • Page 197 HT66F60A/HT66F70A A/D Flash MCU with EEPROM MFI2 Register Name SIMF T3�F T3PF SIME T3�E T3PE SIMF: SIM interrupt request flag Bit 7 0: No request 1: Interrupt request XPF: External peripheral interrupt request flag Bit 6 0: No request 1: Interrupt request T3AF: TM3 Comparator A match interrupt request flag Bit 5 0: No request 1: Interrupt request T3PF: TM3 Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request SIME: SIM Interrupt Control Bit 3 0: Disable 1: Enable XPE: External peripheral Interrupt Control Bit 2 0: Disable 1: Enable T3AE: TM3 Comparator A match interrupt control...
  • Page 198 HT66F60A/HT66F70A A/D Flash MCU with EEPROM MFI3 Register Name — SPI�F — SPI�E — — — — Bit 7 Unimplemented, read as “0” Bit 6 SPIAF: SPIA interrupt request flag 0: No request 1: Interrupt request Bit 5 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request LVF: LVD interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3 Unimplemented, read as “0” SPIAE: SPIA Interrupt Control Bit 2 0: Disable 1: Enable DEE: Data EEPROM Interrupt Control Bit 1 0: Disable...
  • Page 199 HT66F60A/HT66F70A A/D Flash MCU with EEPROM MFI4 Register Name T5�F T5PF T4�F T4PF T5�E T5PE T4�E T4PE T5AF: TM5 Comparator A match interrupt request flag Bit 7 0: No request 1: Interrupt request T5PF: TM5 Comparator P match interrupt request flag Bit 6 0: No request 1: Interrupt request T4AF: TM4 Comparator A match interrupt request flag Bit 5 0: No request 1: Interrupt request T4PF: TM4 Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request T5AE: TM5 Comparator A match interrupt control Bit 3 0: Disable 1: Enable T5PE: TM5 Comparator P match interrupt control Bit 2 0: Disable...
  • Page 200 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Interrupt Operation EMI a�to disabled in ISR Legend Req�est Fla�� no a�to reset in ISR Interr�pt Req�est Enable Master Vector Priority Req�est Fla�� a�to reset in ISR Name Fla�s Bits Enable Hi�h INT0 Pin...
  • Page 201 HT66F60A/HT66F70A A/D Flash MCU with EEPROM External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT3. An external interrupt request will take place when the external interrupt request flags, INT0F~INT3F are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT3E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT3F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt The comparator interrupts are controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flags, CP0F or CP1F, are set, a situation that will occur when the comparator output changes state. To allow the program to branch...
  • Page 202 HT66F60A/HT66F70A A/D Flash MCU with EEPROM A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts.
  • Page 203 HT66F60A/HT66F70A A/D Flash MCU with EEPROM PSC0 Register Name — — — — — — CLKS01 CLKS00 — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 CLKS01~CLKS00: Time Base clock source Selection 00: f 01: f 10: f 11: f TBC0 Register Name TB0ON —...
  • Page 204 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Serial Interface Module Interrupts The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. SPIA Interface Interrupt The SPIA Interface Interrupt is contained within the Multi-function Interrupt. A SPIA Interrupt request will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the SPIA Interface Interrupt enable bit, SPIAE, and Muti-function interrupt enable bits, must first be set. When the...
  • Page 205 HT66F60A/HT66F70A A/D Flash MCU with EEPROM EEPROM Interrupt The EEPROM Interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program.
  • Page 206 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program.

  • Page 207: Low Voltage Detector - Lvd

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, V , and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the V voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Name — — LVDO LVDEN — VLVD� VLVD1 VLVD0 —...

  • Page 208: Lvd Operation

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, V , with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, V , falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay t should be allowed for the circuitry to stabilise before reading the LVDS LVDO bit. Note also that as the V voltage may rise and fall rather slowly, at the voltage nears that of V , there may be multiple bit LVDO transitions. V D D L V D L V D E N L V D O L V D S...

  • Page 209: Scom Function For Lcd

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM SCOM Function for LCD The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with the PC0~PC1, PC6~PC7 pins. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using this device by configuring the PC0~PC1, PC6~PC7 pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary V /2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. S C O M o p e r a t i n g c u r r e n t...

  • Page 210: Configuration Options

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Configuration Options Configuration options refer to certain options within the MCU that are programmed into the devices during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the devices using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. Options Hi�h Speed System Oscillator Selection – f HXT� ERC or HIRC Low Speed System Oscillator Selection – f � LXT or LIRC I/O or Reset pin selection...

  • Page 211: Instruction Set

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers...

  • Page 212: Branches And Control Transfer

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...

  • Page 213: Instruction Set Summary

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory section 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic �DD ��[m] �dd Data Memory to �CC Z� C� �C� OV� SC �DDM ��[m] �dd �CC to Data Memory Note Z�...
  • Page 214 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Data Move MOV ��[m] Move Data Memory to �CC None MOV [m]�� Move �CC to Data Memory Note None MOV ��x Move immediate data to �CC None Bit Operation CLR [m].i...

  • Page 215: Extended Instr�Ction Set

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except section 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic L�DD ��[m] �dd Data Memory to �CC �...
  • Page 216 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Branch LSZ [m] Skip if Data Memory is zero � Note None LSZ� [m] Skip if Data Memory is zero with data movement to �CC � Note None LSNZ [m] Skip if Data Memory is not zero �...

  • Page 217: Instruction Definition

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC ADD A,x...
  • Page 218 HT66F60A/HT66F70A A/D Flash MCU with EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared.
  • Page 219 HT66F60A/HT66F70A A/D Flash MCU with EEPROM CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ← [m] − 1...
  • Page 220 HT66F60A/HT66F70A A/D Flash MCU with EEPROM JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
  • Page 221 HT66F60A/HT66F70A A/D Flash MCU with EEPROM RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s) None RLA [m]...
  • Page 222 HT66F60A/HT66F70A A/D Flash MCU with EEPROM RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None Rotate Data Memory right through Carry RRC [m] Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0...
  • Page 223 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m]=0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH...
  • Page 224 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SNZ [m] Skip if Data Memory is not 0 Description If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m]≠ 0 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ SUB A,x...
  • Page 225 HT66F60A/HT66F70A A/D Flash MCU with EEPROM SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ← [m] Skip if [m]=0 Affected flag(s) None SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i=0 Affected flag(s) None TABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s)
  • Page 226 HT66F60A/HT66F70A A/D Flash MCU with EEPROM XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″XOR″ [m] Affected flag(s) XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″XOR″ x Affected flag(s) Rev. 1.40 ��6 ����st ��� �01�...

  • Page 227: Extended Instruction Definition

    HT66F60A/HT66F70A A/D Flash MCU with EEPROM Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C, SC LADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C, SC...
  • Page 228 HT66F60A/HT66F70A A/D Flash MCU with EEPROM LCPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ← [m] Affected flag(s) LCPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) LDAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or...
  • Page 229 HT66F60A/HT66F70A A/D Flash MCU with EEPROM LMOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None LMOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ← ACC Affected flag(s) None LOR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ← ACC ″OR″ [m] Affected flag(s) LORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ← ACC ″OR″ [m]...
  • Page 230 HT66F60A/HT66F70A A/D Flash MCU with EEPROM LRR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 Affected flag(s) None LRRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None LRRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) LRRCA [m]...
  • Page 231 HT66F60A/HT66F70A A/D Flash MCU with EEPROM LSDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ← [m] − 1 Skip if [m]=0 Affected flag(s) None LSDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory LSET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH...
  • Page 232 HT66F60A/HT66F70A A/D Flash MCU with EEPROM LSNZ [m] Skip if Data Memory is not 0 Description If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m] ≠ 0 Affected flag(s) None LSUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C, SC, CZ LSWAP [m]...
  • Page 233 HT66F60A/HT66F70A A/D Flash MCU with EEPROM LSZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i=0 Affected flag(s) None LTABRD [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LTABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRD [m]...
  • Page 234 HT66F60A/HT66F70A A/D Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.40 �34 ����st ��� �01�...
  • Page 235 HT66F60A/HT66F70A A/D Flash MCU with EEPROM 48-pin LQFP (7mm×7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. � — 0.354 BSC — — 0.��6 BSC — — 0.354 BSC — — 0.��6 BSC — — 0.0�0 BSC — 0.00�...
  • Page 236 HT66F60A/HT66F70A A/D Flash MCU with EEPROM 64-pin LQFP (7mm×7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. � — 0.354 BSC — — 0.��6 BSC — — 0.354 BSC — — 0.��6 BSC — — 0.016 BSC — 0.005 0.00�...
  • Page 237 �se of its prod�cts for application that may present a risk to h�man life d�e to malf�nction or otherwise. Holtek's prod�cts are not a�thorized for �se as critical components in life s�pport devices or systems. Holtek reserves the ri�ht to alter its products without prior notification. For the most up-to-date information, please visit o�r web site at http://www.holtek.com.

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