Holtek HT67F2350 Manual page 146

Counter Value
CCRP
CCRA
STnON
STnPAU
STnPOL
CCRA Int. flag
STMnAF
CCRP Int. flag
STMnPF
STMn O/P Pin
(STnOC=1)
STMn O/P Pin
(STnOC=0)
PWM Duty Cycle
set by CCRA
Note: 1. Here STnDPX=0 – Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when STnIO [1:0]=00 or 01
4. The STnCCLR bit has no influence on PWM operation
5. n=0 ~ 2
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
Counter cleared by
CCRP
Pause
PWM Period
set by CCRP
PWM Output Mode – STnDPX=0
146
HT67F2350/HT67F2360
HT67F2370/HT67F2390
STnDPX = 0; STnM [1:0] = 10
Counter Reset when
STnON returns high
Counter Stop if
Resume
STnON bit low
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when STnPOL = 1
May 16, 2019
Time