Holtek HT67F2350 Manual page 94

Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT"
instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the
FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions
described above, the following will occur:
• The f clock will be stopped and the application program will stop at the "HALT" instruction, but
H
the f clock will be on.
SUB
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT"
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to "1". When this instruction is executed under the conditions described above, the following
will occur:
• The f and f
H SUB
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
Entering the IDLE2 Mode
There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT"
instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the
FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The f clock will be on but the f
H
"HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be
cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled by the WDTC
register.
Rev. 1.60
Advanced A/D Flash MCU with LCD & EEPROM
clocks will be on but the application program will stop at the "HALT" instruction.
clock will be off and the application program will stop at the
SUB
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HT67F2350/HT67F2360
HT67F2370/HT67F2390
May 16, 2019