Mitsubishi Electric R60AD8-G User Manual page 201

• For the R60AD16-G
Buffer memory name
CH Factory default setting offset value (L)
CH Factory default setting offset value (H)
CH Factory default setting gain value (L)
CH Factory default setting gain value (H)
CH User range setting offset value (L)
CH User range setting offset value (H)
CH User range setting gain value (L)
CH User range setting gain value (H)
When the following operations are performed, the data to be used is stored (saved).
• Writing the initial setting by engineering tool
• Turning off and on 'Operating condition setting request' (Y9) (Data is not saved when the mode is switched from the normal
mode to the offset/gain setting mode by 'Mode switching setting' (Un\G296, Un\G297).)
• Writing an offset/gain value in the offset/gain setting mode (When 'User range write request' (YA) is turned off and on)
When restoring the offset/gain setting value in user range setting, set the same data as the saved data in this area to the
corresponding area of the A/D converter module that is the restoration destination.
For the offset/gain setting, refer to the following.
 MELSEC iQ-R Channel Isolated Analog-Digital Converter Module User's Manual (Startup)
■Default value
The default value is 0 for all channels.
Address
CH1 CH2 CH3
4004 4008 4012
CH9 CH10 CH11
4036 4040 4044
CH1 CH2 CH3
4005 4009 4013
CH9 CH10 CH11
4037 4041 4045
CH1 CH2 CH3
4006 4010 4014
CH9 CH10 CH11
4038 4042 4046
CH1 CH2 CH3
4007 4011 4015
CH9 CH10 CH11
4039 4043 4047
CH1 CH2 CH3
4068 4072 4076
CH9 CH10 CH11
4100 4104 4108
CH1 CH2 CH3
4069 4073 4077
CH9 CH10 CH11
4101 4105 4109
CH1 CH2 CH3
4070 4074 4078
CH9 CH10 CH11
4102 4106 4110
CH1 CH2 CH3
4071 4075 4079
CH9 CH10 CH11
4103 4107 4111
CH4 CH5 CH6
4016 4020 4024
CH12 CH13 CH14
4048 4052 4056
CH4 CH5 CH6
4017 4021 4025
CH12 CH13 CH14
4049 4053 4057
CH4 CH5 CH6
4018 4022 4026
CH12 CH13 CH14
4050 4054 4058
CH4 CH5 CH6
4019 4023 4027
CH12 CH13 CH14
4051 4055 4059
CH4 CH5 CH6
4080 4084 4088
CH12 CH13 CH14
4112 4116 4120
CH4 CH5 CH6
4081 4085 4089
CH12 CH13 CH14
4113 4117 4121
CH4 CH5 CH6
4082 4086 4090
CH12 CH13 CH14
4114 4118 4122
CH4 CH5 CH6
4083 4087 4091
CH12 CH13 CH14
4115 4119 4123
Appendix 3 Buffer Memory Areas
CH7 CH8
4028 4032
CH15 CH16
4060 4064
CH7 CH8
4029 4033
CH15 CH16
4061 4065
CH7 CH8
4030 4034
CH15 CH16
4062 4066
CH7 CH8
4031 4035
CH15 CH16
4063 4067
CH7 CH8
4092 4096
CH15 CH16
4124 4128
CH7 CH8
4093 4097
CH15 CH16
4125 4129
CH7 CH8
A
4094 4098
CH15 CH16
4126 4130
CH7 CH8
4095 4099
CH15 CH16
4127 4131
APPX
199