Mitsubishi Electric R60AD8-G User Manual page 149

Latest address of alarm history
Among Alarm history  (Un\G3760 to Un\G3999), a buffer memory address which stores the latest alarm code is stored.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Latest address of alarm history
Latest address of alarm history (in Q compatible
mode)
Interrupt factor detection flag [n]
The detection status of the interrupt factor is stored.
Monitor value
0
1
When an interrupt factor occurs, an interrupt request is sent to the CPU module at the same time as 'Interrupt factor detection
flag [n]' (Un\G4 to Un\G19) is turned to Interrupt factor (1).
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name 1
Interrupt factor detection flag 4
[n]
Interrupt factor detection flag 4000
[n] (in Q compatible mode)
Alert output flag (Process alarm upper limit)
The upper limit alarm of the process alarm can be checked for each channel.
b15 b14 b13 b12 b11 b10 b9
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
• 0: Normal, 1: Alarm ON
• b8 to b15 of the R60AD8-G are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Alert output flag (Process alarm upper limit)
■Alert output flag status
• When the value is out of the range specified in the process alarm upper upper limit value, Alarm ON (1) is stored in 'Alert
output flag (Process alarm upper limit)' (Un\G36) corresponding to each channel.
• When an alert is detected in any channel where the A/D conversion and the alert output setting (Process alarm) are
enabled, 'Alert output signal' (X8) also turns on.
■Clearing Alert output flag
• When the digital operation value returns within the setting range, the flag is automatically cleared.
• When 'Operating condition setting request' (Y9) is turned on and off, the flag is cleared.
CH CH CH CH
1 2 3 4
3
3751
2 3 4 5 6
5 6 7 8 9
4001 4002 4003 4004 4005
b8 b7 b6 b5 b4 b3 b2
CH8 CH7 CH6 CH5 CH4 CH3
CH CH CH CH
1 2 3 4
36
CH CH CH CH CH
5 6 7 8 9

Description
No interrupt factor
Interrupt factor
7 8 9 10
10 11 12 13
4006 4007 4008 4009
b1 b0
CH2 CH1
CH CH CH CH CH
5 6 7 8 9
CH CH CH CH CH CH
10 11 12 13 14 15
11 12 13 14 15
14 15 16 17 18
4010 4011 4012 4013 4014
CH CH CH CH CH CH
10 11 12 13 14 15
APPX
Appendix 3 Buffer Memory Areas
CH
16
16
19
4015
A
CH
16
147