Mitsubishi Electric R60AD8-G User Manual page 183

Melsec iq-r series channel isolated analog-digital converter module
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CH1 Rate alarm alert detection cycle setting
Set the cycle to check the change rate of digital output values.
The value of the cycle to detect a rate alarm alert is the product of the value in 'CH1 Rate alarm alert detection cycle setting'
(Un\G522) and the conversion cycle.
■Buffer memory address
The following shows the buffer memory address of this area.
• CH Rate alarm alert detection cycle setting
CH1
CH2
CH3
CH4
522
722
922
1122
• CH Rate alarm alert detection cycle setting (in Q compatible mode)
CH1
CH2
CH3
CH4
118
119
120
121
■Setting range
The setting range is from 1 to 32000 (times).
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9).
■Default value
The default value is 0 for all channels.
• In the channel where a value out of the range is set, a rate alarm detection cycle setting range error (error
code: 1B9H) occurs.
• Since the default value is 0, change the setting value when setting the rate alarm function.
CH1 Rate alarm upper limit value
Set an upper limit value of the change rate of digital output values to detect a rate alarm.
For details on the alert output function, refer to the following.
Page 30 Alert Output Function
■Buffer memory address
The following shows the buffer memory address of this area.
• CH Rate alarm upper limit value
CH1
CH2
CH3
CH4
524
724
924
1124
• CH Rate alarm upper limit value (in Q compatible mode)
CH1
CH2
CH3
CH4
126
128
130
132
■Setting range
The setting range is from -32768 to 32767 (-3276.8 to 3276.7%). (Set it in a unit of 0.1%.)
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9).
■Default value
The default value is 0 for all channels.
CH5
CH6
CH7
CH8
1322
1522
1722
1922
CH5
CH6
CH7
CH8
122
123
124
125
CH5
CH6
CH7
CH8
1324
1524
1724
1924
CH5
CH6
CH7
CH8
134
136
138
140
CH9
CH10
CH11
CH12
2122
2322
2522
2722
CH9
CH10
CH11
CH12
CH9
CH10
CH11
CH12
2124
2324
2524
2724
CH9
CH10
CH11
CH12
Appendix 3 Buffer Memory Areas
CH13
CH14
CH15
CH16
2922
3122
3322
3522
CH13
CH14
CH15
CH16
CH13
CH14
CH15
CH16
2924
3124
3324
3524
CH13
CH14
CH15
CH16
APPX
A
181

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