Slave Wait Release (Transmission) - NEC PD78076 User Manual

CHAPTER 18
(2) Slave wait release (slave transmission)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the
clock rises without the start transmission bit being output in the data line. Therefore, manipulate the P27
output latch through the program as shown in Figure 18-25 to transmit data correctly. At this time, control the
low-level width ("a" in Figure 18-25) of the first serial clock at the timing used for setting the P27 output latch
to 1 after execution of an SIO0 write instruction.
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is
completed), set 1 in the WREL flag of SINT and release the wait.
For these timings, see Figure 18-23.
Master device operation
Software operation
Hardware operation
Transfer line
SCL
SDA0 (SDA1)
A0
Slave device operation
Software operation
Hardware operation
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
Figure 18-25. Slave Wait Release (Transmission)
Setting Setting
ACKD CSIIF0
9
R ACK
ACK Setting
output CSIIF0
Writing
FFH
to SIO0
a
1
D7
P27
Write P27
output data output
latch 0 to SIO0 latch 1
Wait
release
Serial reception
2 3
D6 D5
Serial transmission
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