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CHAPTER 18
(3) Slave wait release (slave reception)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to
SIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannot
start operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0
(until the next instruction execution is started). Therefore, manipulate the P27 output latch through the program
as shown in Figure 18-26 to receive data correctly.
For these timings, see Figure 18-22.
Master device operation
Software operation
Hardware operation
Transfer line
SCL
SDA0 (SDA1)
Slave device operation
Software operation
Hardware operation
(4) Reception completion of slave
During processing of reception completion by a slave device, confirm the statuses of CMDD and COI (if
CMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount of
data is sent from the master device, the slave device cannot determine whether the start condition signal or
the data will be sent from the master. This may disable use of the wake-up function.
410
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
Figure 18-26. Slave Wait Release (Reception)
Setting
Setting
ACKD
CSIIF0
9
A0
W
ACK
ACK
Setting
output
CSIIF0
Writing
data
to SIO0
1
D7
P27
P27
Write
output
FFH
output
to SIO0
latch 1
latch 0
Wait
release
Serial transmission
2
3
D6
D5
Serial reception
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