Clock Generator Operations - NEC PD78076 User Manual

7.5 Clock Generator Operations

The clock generator generates the following various types of clocks and controls the CPU operating mode
including the standby mode.
• Main system clock f
• Subsystem clock f
XT
• CPU clock f
CPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined with the processor clock control register
(PCC) and the oscillation mode selection register (OSMS).
(a) Upon generation of RESET signal, the lowest speed mode of the main system clock (12.8 s when operated
at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while the low level
is applied to RESET pin.
(b) With the main system clock selected, one of the five CPU clock stages (f
be selected by setting the PCC and OSMS.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. In a
system which is not using the subsystem clock, the current consumption in the STOP mode can be reduced
further by setting bit 6 (FRC) of the PCC so as not to use the on-chip feedback resistor.
(d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption
(122 s when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT
mode can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be
stopped.)
(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied
to 16-bit timer/event counter, the watch timer, and clock output functions only. Thus, 16-bit timer/event counter
(when selecting watch timer output for count clock operating with subsystem clock), the watch function, and
the clock output function can also be continued in the standby state. However, since all other peripheral
hardware operate with the main system clock, the peripheral hardware also stops if the main system clock
is stopped. (Except external input clock operation)
CHAPTER 7 CLOCK GENERATOR
XX
, f /2, f /2 2 , f /2 3 or f /2
XX XX XX XX XX
4 ) can
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