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CHAPTER 18
Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both
Master and Slave) (1/3)
Processing in master device
SIO0 write
COI
ACKD
CMDD
L
RELD
CLD
P27
H
L
WUP
BSYE
ACKE
CMDT
L
RELT
CLC
L
WREL
L
SIC
INTCSI0
Transfer line
SCL
SDA0
Processing in slave device
SIO0 write
COI
ACKD
CMDD
L
RELD
CLD
P27
WUP
BSYE
ACKE
L
CMDT
L
RELT
L
CLC
L
WREL
H
SIC
INTCSI0
CSIE0
H
L
P25
L
PM25
L
PM27
404
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
(a) Start condition - address
SIO0 <- address
1
2 3 4 5 6 7 8
9
A6
A5
A4
A3
A2
A1
A0
R ACK
SIO0 <- FFH
1
2
3 4 5
D7
D6
D5 D4 D3
SIO0 <- data
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