Various Signals In Sbi Mode - NEC PD78076 User Manual

Pd78078 series; pd78078y series 8-bit single-chip microcontrollers
Table of Contents

Advertisement

Output
Signal Name
Definition
Device
Bus release
SB0 (SB1) rising edge
signal
Master
when SCK0 = 1
(REL)
Command
SB0 (SB1) falling edge
signal
Master
when SCK0 = 1
(CMD)
Low-level signal to be
Acknowledge
output to SB0 (SB1) during
Master/
signal
one-clock period of SCK0
slave
(ACK)
after completion of serial
reception
[Synchronous BUSY signal]
Low-level signal to be
Busy signal
Slave
output to SB0 (SB1)
(BUSY)
following Acknowledge
signal
High-level signal to be
output to SB0 (SB1)
Ready signal
Slave
before serial transfer start
(READY)
and after completion of
serial transfer
Table 17-3. Various Signals in SBI Mode (1/2)
Timing Chart
SCK0
"H"
SB0 (SB1)
SCK0
"H"
SB0 (SB1)
[Synchronous BUSY output]
SCK0
9
ACK
BUSY
SB0 (SB1)
D0
ACK
SB0 (SB1)
D0
Output
Condition
• RELT set
• CMDT set
(1) ACKE = 1
(2) ACKT set
• BSYE = 1
READY
BUSY
(1) BSYE = 0
READY
(2) Execution of
instruction for
data write to
SIO0
(transfer start
instruction)
Effects on Flag
Meaning of Signal
CMD signal is output
• RELD set
to indicate that
• CMDD clear
transmit data is an
address.
i) Transmit data is an
address after REL
signal output.
• CMDD set
ii) REL signal is not
output and trans-
mit data is an
command.
Completion of
• ACKD set
reception
Serial receive disable
because of
processing
Serial receive enable

Advertisement

Table of Contents
loading

Table of Contents