Special Function Register (Sfr) - NEC PD78076 User Manual

5.2.3 Special function register (SFR)

Unlike a general register, each special function register has special functions.
It is allocated in the FF00H to FFFFH area.
The special function registers can be manipulated in a similar way as the general registers, by using operation,
transfer, or bit-manipulate instructions. The special function regsters are read from and written to in specified
manipulation bit units (1, 8, and/or 16) depending on the register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).
When addressing an address, describe an even address.
Table 5-3 gives a list of special function registers. The meaning of items in the table is as follows.
• Symbol
This column shows the addresses of the special function registers.
They have been defined as reserved words in the RA78K/0 and as the header file, sfrbit.h, in the CC78K/0.
They can be described as instruction operands when the RA78K/0, ID78K0-NS, ID78K0, and SM78K/0 are used.
• R/W
This column shows whether the corresponding special function register can be read or written.
R/W : Both reading and writing are enabled.
R : The value in the register can read out. A write to this register is ignored.
W : A value can be written to the register. Reading values from the register is impossible.
• Manipulation
The register can be manipulated in bit units marked with a check ( ) mark.
The register cannot be manipulated in bit units marked with "—".
• After reset
The register is set to the value immediately after the RESET signal is input.
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CHAPTER 5 CPU ARCHITECTURE