Operation Timing With Automatic Data Transmit/Receive Function Performed By Internal Clock; Interval Timing Through Cpu Processing (When The Internal Clock Is Operating) - NEC PD78076 User Manual

(a) When the automatic transmit/receive function is used by the internal clock
If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates.
If the automatic transmit/receive function is operated by the internal clock, interval timing by CPU
processing is as follows.
When bit 7 (ADTI7) of automatic data transmit/receive interval specify register (ADTI) is set to 0, the
interval depends on the CPU processing. When ADTI7 is set to 1, it depends on the contents of the
ADTI or CPU processing, whichever is greater.
Refer to Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format for the
intervals which are set by the ADTI.
Table 19-2. Interval Timing through CPU Processing (when the Internal Clock is Operating)
CPU Processing
When using multiplication instruction
When using division instruction
External access 1 wait mode
Other than above
T : 1/f
SCK SCK
f : Serial clock frequency
SCK
T : 1/f
CPU CPU
f : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
CPU
and bit 0 (MCS) of the oscillation mode selection register (OSMS))
MAX. (a, b) : a or b, whichever is greater
Figure 19-24. Operation Timing with Automatic Data Transmit/Receive Function Performed by
Internal Clock
f
X
T
CPU
f
CPU
T
SCK
SCK1
SO1 D7 D6
SI1 D7 D6
f : Main system clock oscillation frequency
X
f : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) and
CPU
bit 0 (MCS) of the oscillation mode selection register (OSMS).
T : 1/f
CPU CPU
T : 1/f
SCK SCK
f : Serial clock frequency
SCK
CHAPTER 19 SERIAL INTERFACE CHANNEL 1
D5 D4 D3
D5 D4 D3
Interval Time
Max. (2.5T , 13T )
SCK CPU
Max. (2.5T , 20T )
SCK CPU
Max. (2.5T , 9T )
SCK CPU
Max. (2.5T , 7T )
SCK CPU
D2 D1
D2 D1
Interval
D0
D0
455