Figure No.
7-1
Block Diagram of Clock Generator ............................................................................................ 166
7-2
7-3
7-4
7-5
7-6
External Circuit of Main System Clock Oscillator ..................................................................... 171
7-7
External Circuit of Subsystem Clock Oscillator ......................................................................... 172
7-8
7-9
7-10
System Clock and CPU Clock Switching .................................................................................. 179
8-1
8-2
8-3
8-4
8-5
8-6
16-Bit Timer Output Control Register Format ........................................................................... 194
8-7
Port Mode Register 3 Format ..................................................................................................... 195
8-8
External Interrupt Mode Register 0 Format ............................................................................... 196
8-9
Sampling Clock Select Register Format .................................................................................... 197
8-10
8-11
8-12
Interval Timer Operation Timings .............................................................................................. 199
8-13
8-14
8-15
8-16
8-17
Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ......................................................................................................... 204
8-18
8-19
Timing of Pulse Width Measurement Operation by Free-Running Counter and
One Capture Register (with Both Edges Specified) ................................................................. 205
8-20
Control Register Settings for Two Pulse Width Measurements with
Free-Running Counter ................................................................................................................ 206
8-21
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ....................................................................................................... 207
8-22
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers ............................................................................................................... 208
8-23
Timing of Pulse Width Measurement Operation by Free-Running Counter and
Two Capture Registers (with Rising Edge Specified) ............................................................... 209
8-24
8-25
Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) ...................................................................................................... 210
22
LIST OF FIGURES (2/9)
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