I 2 C Bus Serial Data Transfer Timing - NEC PD78076 User Manual

CHAPTER 18
(1) I 2 C bus mode functions
In the I 2 C bus mode, the following functions are available.
(a) Automatic identification of serial data
Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in
series through the serial data bus.
(b) Chip selection by specifying device addresses
The master device can select a specific slave device connected to the I
by sending in advance the address data corresponding to the destination device.
(c) Wake-up function
When address data is sent from the master device, slave devices compare it with the value registered in
their internal slave address registers. If the values in one of the slave devices match, the slave device
internally generates an interrupt request signal to terminate the current processing and communicates
with the master device (an interrupt request generates also when a stop condition is detected). Therefore,
CPUs other than the selected slave device on the I
communication.
(d) Acknowledge signal (ACK) control function
The master device and a slave device send and receive acknowledge signals to confirm that the serial
communication has been executed normally.
(e) Wait signal (WAIT) control function
When a slave device is preparing for data transmission or reception and requires more waiting time, the
slave device outputs a wait signal on the bus to inform the master device of the wait status.
2
(2) I C bus definition
This section describes the format of serial data communications and functions of the signals used in the I
bus mode.
First, the transfer timings of the start condition, data, and stop condition signals, which are output onto the
signal data bus of the I
SCL
SDA0 (SDA1)
Start
condition
The start condition, slave address, and stop condition signals are output by the master. The acknowledge
signal (ACK) is output by either the master or the slave device (normally by the device which has received
the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device.
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
2 C bus, are shown in Figure 18-14.
Figure 18-14. I 2 C Bus Serial Data Transfer Timing
1-7 8 9 1-7
Address R/W ACK
2 C bus and communicate with it
2
C bus can operate independently during the serial
8 9 1-7
Data ACK Data
2 C
8 9
ACK Stop
condition
391