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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78078 SUBSERIES)
R
ACKD
Acknowledge Detection
Clear Conditions (ACKD = 0)
• SCK0 fall immediately after the busy mode is
released during the transfer start instruction execution.
• When CSIE0 = 0
• When RESET input is applied
R/W
Note
BSYE
Synchronizing Busy Signal Output Control
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
0
execution of the instruction to be cleared to (0) (sets ready state).
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
Note Busy mode can be cleared by start of serial interface transfer. However, BSYE flag is not cleared
to 0.
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)
342
Set Conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
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