Stop Mode - NEC PD78076 User Manual

24.2.2 STOP mode

(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V
resistor to minimize leakage current at the crystal oscillator. Thus, do not use the STOP
mode in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to release the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction. After the wait set
using the oscillation stabilization time select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
STOP Mode Setting
Item
Clock Generator
CPU
Port (output latch)
16-bit timer/event counter
8-bit timer/event counters 1 and 2
8-bit timer/event counters 5 and 6
Watch timer
Watchdog timer
A/D converter
D/A converter
Real-time output port
Serial Interface
When a function other than auto
transmit/receive & UART is used
When auto transmit/receive
function or UART is used
External interrupt
INTP0
INTP1 to INTP6
Bus lines in external expansion
AD0 to AD7
A0 to A15
ASTB
WR, RD
WAIT
550
CHAPTER 24 STANDBY FUNCTION
Table 24-3. STOP Mode Operating Status
With Subsystem Clock
Only main system clock stops oscillation.
Operation stops.
Status before STOP mode setting is held.
Operable when watch timer output is used
as count clock (f is selected as count
XT
clock for watch timer).
Operable when TI1 or TI2 is selected for the count clock.
Operable when TI5 or TI6 is selected for the count clock.
Operable when f is selected for the count clock.
XT
Operation stops.
Operation stops.
Operable.
Operable when external trigger is used, or TI1 or TI2 is selected for the 8-bit timer/
event counter 1 or 2 count clock.
Operable only when externally supplied clock is specified as the serial clock.
Operation stops.
Operation disabled.
Operable.
Enters high-impedance state.
Holds the state before STOP mode is set.
Outputs low level.
Outputs high level.
Enters high-impedance state.
via a pull-up
DD
Without Subsystem Clock
Operation stops.
Operation stops.