NEC PD78076 User Manual page 400

CHAPTER 18
(6) Address match detection method
In the I 2 C mode, the master can select a specific slave device by sending slave address data.
Address match detection is performed automatically by the slave device hardware. A slave device address has
a slave register (SVA), and compares its contents and the slave address sent from the master device. If they
match and the wake-up function specification (WUP) bit is then 1, CSIIF0 is set (also when a stop condition is
detected).
When using the wake-up function, set SIC to 1.
Caution Whether a slave is selected or not is detected by the matching of the data (address) received
after start condition.
The matching detection interrupt request (INTCSI0) of the address generated in the WUP =
1 state is normally used for detecting the matching of the data. Therefore, detection of
whether a slave is selected or not using slave address must be performed in the WUP = 1
state.
(7) Error detection
2
In the I C bus mode, transmission error can be detected by the following methods because the serial bus SDA0
(SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) of the transmitting device.
(a) Comparison of SIO0 data before and after transmission
In this case, a transmission error is judged to have occurred if the two data values are different.
(b) Using the slave address register (SVA)
Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit
(match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1"
indicates normal transmission, and "0" indicates a transmission error.
(8) Communication operation
In the I 2 C bus mode, the master selects the slave device to be communicated with from among multiple
devices by outputting address data onto the serial bus.
After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and
starts serial communication with the selected slave device.
Data communication timing charts are shown in Figures 18-22 and 18-23.
In the transmitting device, the serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in
synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-first
basis from the SDA0 or SDA1 pin to the receiving device.
In the receiving device, the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchronization
with the rising edge of SCL.
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SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)