Figure No.
18-10
18-11
18-12
RELT and CMDT Operations ..................................................................................................... 389
18-13
Example of Serial Bus Configuration Using I
18-14
I
2
C Bus Serial Data Transfer Timing ......................................................................................... 391
18-15
Start Condition ............................................................................................................................ 392
18-16
Address ....................................................................................................................................... 392
18-17
18-18
Acknowledge Signal ................................................................................................................... 393
18-19
Stop Condition ............................................................................................................................ 393
18-20
Wait Signal .................................................................................................................................. 394
18-21
Pin Configuration ........................................................................................................................ 399
18-22
Example of Communication from Master to Slave
(with 9-Clock Wait Selected for Both Master and Slave) ......................................................... 401
18-23
Example of Communication from Slave to Master
(with 9-Clock Wait Selected for Both Master and Slave) ......................................................... 404
18-24
Start Condition Output ................................................................................................................ 408
18-25
18-26
18-27
SCK0/SCL/P27 Pin Configuration .............................................................................................. 413
18-28
18-29
Logic Circuit of SCL Signal ........................................................................................................ 414
19-1
19-2
19-3
19-4
19-5
Automatic Data Transmit/Receive Interval Specify Register Format ....................................... 421
19-6
19-7
Circuit of Switching in Transfer Bit Order .................................................................................. 428
19-8
19-9
19-10
Buffer RAM Operation in 6-byte Transmission/Reception
(in Basic Transmit/Receive Mode) ............................................................................................. 438
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
26
LIST OF FIGURES (6/9)
Title
2
C Bus ................................................................ 390
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