Table of Contents
Advertisement
28.2 Operation List
Instruction Mnemonic
Group
8-bit data
MOV
r, #byte
transfer
saddr, #byte
sfr, #byte
Note 3
A, r
Note 3
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
Note 3
XCH
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. For instructions that access the internal high-speed RAM area or perform no data access
2. For instructions that access an area other than the internal high-speed RAM area
3. Except when "r = A"
Remarks 1. One clock in the "Clock" columns is equal to one cycle of the CPU clock (f
clock control register (PCC).
2. The values in the "Clock" column assumes that the internal ROM area contains programs.
3. n indicates wait cycles to be inserted when an external expansion memory area is read from.
4. m indicates wait cycles to be inserted when an external expansion memory area is written to.
584
CHAPTER 28 INSTRUCTION SET
Operands
Byte
Clock
Note 1 Note 2
2
4
3
6
3
—
1
2
1
2
2
4
2
4
2
—
2
—
3
8
3
8
3
—
2
—
2
—
1
4
1
4
1
4
1
4
2
8
2
8
1
6
1
6
1
6
1
6
1
2
2
4
2
—
3
8
10
1
4
1
4
2
8
10
2
8
10
2
8
10
Operation
—
r
byte
7
(saddr)
byte
7
sfr
byte
—
A
r
—
r
A
5
A
(saddr)
5
(saddr)
A
5
A
sfr
5
sfr
A
9 + n
A
(addr16)
9 + m
(addr16)
A
7
PSW
byte
5
A
PSW
5
PSW
A
5 + n
A
(DE)
5 + m
(DE)
A
5 + n
A
(HL)
5 + m
(HL)
A
9 + n
A
(HL + byte)
9 + m
(HL + byte)
A
7 + n
A
(HL + B)
7 + m
(HL + B)
A
7 + n
A
(HL + C)
7 + m
(HL + C)
A
—
A
r
6
A
(saddr)
6
A
sfr
+n+m
A
(addr16)
6
A
(DE)
+n+m
6
A
(HL)
+n+m
A
(HL + byte)
+n+m
+n+m
A
(HL + B)
A
(HL + C)
+n+m
Flag
Z AC CY
x
x
x
x
x
x
) selected by the processor
CPU
Advertisement
Table of Contents
