Restrictions In I C Bus Mode; Restrictions In I 2 C Bus Mode - NEC PD78076 User Manual

CHAPTER 18
18.4.6 Restrictions in I 2 C bus mode
The following restrictions apply to the PD78078Y Subseries.
• Restrictions when used as slave device in I
Applicable models
Description
Preventive measure
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
2 C bus mode
PD78076Y, 78078Y, 78P078Y, and IE-78078-R-EM
When the wake-up function is executed (by setting the WUP flag (bit 5 of the serial
operation mode register 0 (CSIM0)) in the serial transfer status
other slaves and master will be judged as an address. If this data happens to coincide
with the slave address of the PD78078Y Subseries, the PD78078Y Subseries will
initiate communication, destroying the communication data.
Note The serial transfer status is the status in which the interrupt request flag (CSIIF0)
is set because of the end of serial transfer after the serial I/O shift register 0
(SIO0) has been written.
This restriction can be avoided by modifying the program.
Before executing the wake-up function, execute the following program that releases serial
transfer status. To execute the wake-up function, do not execute an instruction that
writes SIO0. Even if such an instruction is not executed, data can be received when the
wake-up function is executed.
This program releases the serial transfer status. To release the serial transfer status,
the serial interface channel 0 must be set once in the operation stop status (by clearing
the CSIE0 flag (bit 7 of the serial operation mode register (CSIM0) to 0). However, if the
serial interface channel 0 is set in the operation stop status in the I
pin output a high level and the SDA0 (SDA1) pin outputs a low level, affecting
2
communication of the I C bus. Therefore, this program places the SCL and SDA0 (SDA1)
pins in the high-impedance state to prevent the I
In the example below, SDA0 (/P25) is used as a serial data input/output pin. When
SDA1 (/P26) is used as the serial data input/output pin, take P2.5 and PM2.5 in the
program below as P2.6 and PM2.6, respectively
For the timing of each signal when this program is executed, refer to Figure 18-22.
Note , data between the
2 C bus mode, the SCL
2
C bus from being affected.
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