System Clock And Cpu Clock Switching Procedure - NEC PD78076 User Manual

7.6.2 System clock and CPU clock switching procedure

This section describes switching procedure between system clock and CPU clock.
V
DD
RESET
Interrupt
Request
Signal
System Clock
CPU Clock
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation
17
stabilization time (2
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 s when
operated at 5.0 MHz).
(2) After the lapse of a sufficient time for the V
the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and
the maximum-speed operation is carried out.
(3) Upon detection of a decrease of the V
is switched to the subsystem clock (which must be in an oscillation stable state).
(4) Upon detection of V
oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation,
the PCC and OSMS are rewritten and the maximum-speed operation is resumed.
Caution When subsystem clock is being operated while main system clock was stopped, if switching
to the main system clock is made again, be sure to switch after securing oscillation stable time
by software.
CHAPTER 7 CLOCK GENERATOR
Figure 7-10. System Clock and CPU Clock Switching
f
XX
Minimum Maximum Speed
Speed Operation
Operation
Wait (26.2 ms : 5.0 MHz)
Internal Reset Operation
/f ) is secured automatically.
X
voltage to increase to enable operation at maximum speeds,
DD
voltage due to an interrupt request signal, the main system clock
DD
voltage reset due to an interrupt request signal, 0 is set to bit 7 (MCC) of PCC and
DD
f f
XX XT
Subsystem Clock
Operation
f
XX
High-Speed
Operation
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