External Memory Read Timing In Separate Bus Mode - NEC PD78076 User Manual

CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
Figure 23-10. External Memory Read Timing in Separate Bus Mode
Note
ASTB
RD
AD0 to AD7
A0 to A7
A8 to A15
Note
ASTB
RD
AD0 to AD7
A0 to A7
A8 to A15
Internal Wait Signal
(1-clock wait)
Note
ASTB
RD
AD0 to AD7
A0 to A7
A8 to A15
WAIT
Note In the separate bus mode, use of the address strobe signal is not required though it is output from
the ASTB/P67 pin.
(a) No wait (PW1, PW0 = 0, 0) setting
Lower Address
(b) Wait (PW1, PW0 = 0, 1) setting
Lower Address
(c) External wait (PW1, PW0 = 1, 1) setting
Lower Address
Read Data
Lower Address
Higher Address
Read Data
Lower Address
Higher Address
Read Data
Lower Address
Higher Address
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