Table of Contents
Advertisement
10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers
The following three types of registers are used to control the 8-bit timer/event counters 5 and 6.
• Timer clock select register 5 and 6 (TCL5, TCL6)
• 8-bit timer mode control registers 5 and 6 (TMC5, TMC6)
• Port mode register 10 (PM10)
(1) Timer clock select register 5 (TCL5)
This register sets count clocks of 8-bit timer register 5.
TCL5 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL5 to 00H.
Symbol
7
6
5
0
0
0
TCL5
TCL53 TCL52 TCL51 TCL50
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Other than above
Note When clock is input from the external, timer output (PWM output) cannot be used.
Caution When rewriting TCL5 to other data, stop the timer operation beforehand.
Remarks 1. f
XX
2. f
X
3. TI5
4. MCS : Bit 0 of oscillation mode selection register (OSMS)
5. Figures in parentheses apply to operation with f
254
CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Figure 10-3. Timer Clock Select Register 5 Format
4
3
2
1
0
TCL53 TCL52 TCL51 TCL50
8-bit Timer Register 5 Count Clock Selection
MCS = 1
Note
0
TI5 falling edge
Note
1
TI5 rising edge
2f
0
XX
f
1
f
X
XX
f
/2
0
f
/2
X
XX
2
2
f
/2
1
f
/2
X
XX
3
3
0
f
/2
f
/2
X
XX
4
4
f
/2
f
/2
1
X
XX
5
5
f
/2
f
/2
0
X
XX
6
6
f
/2
1
f
/2
XX
X
7
7
0
f
/2
f
/2
X
XX
8
8
f
/2
f
/2
1
XX
X
9
9
f
/2
0
f
/2
X
XX
11
11
1
f
/2
f
/2
XX
X
Setting prohibited
: Main system clock frequency (f
: Main system clock oscillation frequency
: 8-bit timer register 5 input pin
Address
After Reset
0
FF52H
00H
MCS = 0
(Setting prohibited)
f
(5.0 MHz)
f
(2.5 MHz)
f
(1.25 MHz)
f
(625 kHz)
f
(313 kHz)
f
(156 kHz)
f
(78.1 kHz)
f
(39.1 kHz)
f
(19.5 kHz)
f
(9.8 kHz)
f
(2.4 kHz)
f
or f
/2)
X
X
= 5.0 MHz.
X
R/W
R/W
(5.0 MHz)
X
/2
(2.5 MHz)
X
2
/2
(1.25 MHz)
X
3
/2
(625 kHz)
X
4
/2
(313 kHz)
X
5
/2
(156 kHz)
X
6
/2
(78.1 kHz)
X
7
/2
(39.1 kHz)
X
8
/2
(19.5 kHz)
X
9
/2
(9.8 kHz)
X
10
/2
(4.9 kHz)
X
11
(1.2 kHz)
/2
X
Advertisement
Table of Contents
